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Searched refs:mpll_cfg (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/rockchip/
A Ddw_hdmi-rockchip.c227 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; in dw_hdmi_rockchip_mode_valid() local
232 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { in dw_hdmi_rockchip_mode_valid()
233 if (pclk == mpll_cfg[i].mpixelclock) { in dw_hdmi_rockchip_mode_valid()
408 .mpll_cfg = rockchip_mpll_cfg,
425 .mpll_cfg = rockchip_mpll_cfg,
445 .mpll_cfg = rockchip_mpll_cfg,
463 .mpll_cfg = rockchip_mpll_cfg,
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_link_encoder.c54 static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
186 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0]; in update_cfg_data()
189 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1]; in update_cfg_data()
192 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2]; in update_cfg_data()
195 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3]; in update_cfg_data()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_link_encoder.c59 static struct mpll_cfg dcn2_mpll_cfg[] = {
226 cfg->mpll_cfg = dcn2_mpll_cfg[0]; in update_cfg_data()
229 cfg->mpll_cfg = dcn2_mpll_cfg[1]; in update_cfg_data()
232 cfg->mpll_cfg = dcn2_mpll_cfg[2]; in update_cfg_data()
235 cfg->mpll_cfg = dcn2_mpll_cfg[3]; in update_cfg_data()
A Ddcn20_link_encoder.h246 struct mpll_cfg { struct
290 struct mpll_cfg mpll_cfg; argument
/linux/drivers/gpu/drm/imx/
A Ddw_hdmi-imx.c167 .mpll_cfg = imx_mpll_cfg,
174 .mpll_cfg = imx_mpll_cfg,
/linux/drivers/gpu/drm/sun4i/
A Dsun8i_hdmi_phy.c575 plat_data->mpll_cfg = variant->mpll_cfg; in sun8i_hdmi_phy_set_ops()
623 .mpll_cfg = sun50i_h6_mpll_cfg,
A Dsun8i_dw_hdmi.h156 const struct dw_hdmi_mpll_config *mpll_cfg; member
/linux/include/drm/bridge/
A Ddw_hdmi.h153 const struct dw_hdmi_mpll_config *mpll_cfg; member
/linux/drivers/gpu/drm/bridge/synopsys/
A Ddw-hdmi.c1447 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; in hdmi_phy_configure_dwc_hdmi_3d_tx()

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