Searched refs:mux_val (Results 1 – 18 of 18) sorted by relevance
| /linux/drivers/clk/mmp/ |
| A D | clk-mix.c | 166 mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift); in _set_rate()
280 u32 div_val, mux_val; in mmp_clk_mix_set_rate_and_parent() local
284 mux_val = _get_mux_val(mix, index); in mmp_clk_mix_set_rate_and_parent()
286 return _set_rate(mix, mux_val, div_val, 1, 1); in mmp_clk_mix_set_rate_and_parent()
296 u32 mux_val; in mmp_clk_mix_get_parent() local
313 mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift); in mmp_clk_mix_get_parent()
315 return _get_mux(mix, mux_val); in mmp_clk_mix_get_parent()
353 u32 div_val, mux_val; in mmp_clk_set_parent() local
365 mux_val = _get_mux_val(mix, item->parent_index); in mmp_clk_set_parent()
369 mux_val = _get_mux_val(mix, index); in mmp_clk_set_parent()
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| /linux/drivers/dma/ti/ |
| A D | dma-crossbar.c | 48 u8 mux_val; member
70 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
112 map->mux_val = (u8)dma_spec->args[2]; in ti_am335x_xbar_route_allocate()
118 map->mux_val, map->dma_line); in ti_am335x_xbar_route_allocate()
120 ti_am335x_xbar_write(xbar->iomem, map->dma_line, map->mux_val); in ti_am335x_xbar_route_allocate()
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| /linux/drivers/gpio/ |
| A D | gpio-sodaville.c | 185 u32 mux_val; in sdv_gpio_probe() local
205 ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val); in sdv_gpio_probe()
207 writel(mux_val, sd->gpio_pub_base + GPMUXCTL); in sdv_gpio_probe()
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| /linux/drivers/pinctrl/bcm/ |
| A D | pinctrl-bcm6328.c | 41 unsigned mux_val:2; member
259 .mux_val = mux, \
344 bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); in bcm6328_pinctrl_set_mux()
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| A D | pinctrl-bcm6318.c | 42 unsigned mux_val:2; member
323 .mux_val = mux, \
430 bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); in bcm6318_pinctrl_set_mux()
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| A D | fsl,imx8mm-pinctrl.yaml | 36 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
50 "mux_val" indicates the mux value to be applied.
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| A D | fsl,imx8mn-pinctrl.yaml | 36 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
50 "mux_val" indicates the mux value to be applied.
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| A D | fsl,imx8mp-pinctrl.yaml | 36 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
50 "mux_val" indicates the mux value to be applied.
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| A D | fsl,imx8mq-pinctrl.yaml | 36 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
50 "mux_val" indicates the mux value to be applied.
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| A D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| A D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /linux/drivers/clk/x86/ |
| A D | clk-cgu.h | 185 unsigned int mux_val; member
219 .mux_val = _v, \
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| A D | clk-cgu.c | 128 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); in lgm_clk_register_mux()
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| /linux/drivers/pinctrl/ |
| A D | pinctrl-zynq.c | 70 unsigned int mux_val; member
760 .mux_val = mval, \
768 .mux_val = mval, \
927 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; in zynq_pinmux_set_mux()
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| A D | pinctrl-bm1880.c | 67 u32 mux_val; member
653 .mux_val = mval, \
998 regval |= func->mux_val << mux_offset; in bm1880_pinmux_set_mux()
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