Searched refs:new_clocks (Results 1 – 8 of 8) sorted by relevance
44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in rv1_determine_dppclk_threshold()53 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()58 if (new_clocks->dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()59 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()63 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()72 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()78 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()82 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()91 struct dc_clocks *new_clocks, in ramp_up_dispclk_with_dpp() argument96 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()[all …]
81 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks_vbios() local87 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn201_update_clocks_vbios()92 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn201_update_clocks_vbios()127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks() local154 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()157 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn201_update_clocks()161 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()168 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn201_update_clocks()178 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn201_update_clocks()183 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in dcn201_update_clocks()[all …]
260 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn2_update_clocks()264 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()312 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz; in dcn2_update_clocks()315 …new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_cl… in dcn2_update_clocks()352 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; in dcn2_update_clocks_fpga()355 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn2_update_clocks_fpga()359 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks_fpga()368 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; in dcn2_update_clocks_fpga()372 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn2_update_clocks_fpga()376 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn2_update_clocks_fpga()[all …]
127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn31_update_clocks() local142 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW && in dcn31_update_clocks()149 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn31_update_clocks()151 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()177 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()190 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn31_update_clocks()202 if (new_clocks->dppclk_khz < 100000) in dcn31_update_clocks()203 new_clocks->dppclk_khz = 100000; in dcn31_update_clocks()207 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in dcn31_update_clocks()209 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn31_update_clocks()[all …]
248 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks() local282 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn3_update_clocks()283 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn3_update_clocks()286 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()291 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()297 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn3_update_clocks()301 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn3_update_clocks()313 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn3_update_clocks()323 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) in dcn3_update_clocks()326 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn3_update_clocks()[all …]
130 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks() local177 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rn_update_clocks()183 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rn_update_clocks()189 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) in rn_update_clocks()190 new_clocks->dppclk_khz = 100000; in rn_update_clocks()196 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()197 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz; in rn_update_clocks()198 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; in rn_update_clocks()202 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) in rn_update_clocks()204 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in rn_update_clocks()[all …]
97 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in vg_update_clocks() local140 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()146 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in vg_update_clocks()152 if (new_clocks->dppclk_khz < 100000) in vg_update_clocks()153 new_clocks->dppclk_khz = 100000; in vg_update_clocks()156 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()157 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()159 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in vg_update_clocks()163 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in vg_update_clocks()164 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in vg_update_clocks()[all …]
354 static const struct snd_ratnum new_clocks[2] = { variable371 .rats = new_clocks,402 if (runtime->rate_num == new_clocks[0].num) in snd_es18xx_rate_set()
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