Searched refs:phy_set_bits (Results 1 – 14 of 14) sorted by relevance
/linux/drivers/net/ethernet/realtek/ |
A D | r8169_phy_config.c | 286 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168bb_hw_phy_config() 307 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168cp_2_hw_phy_config() 308 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168cp_2_hw_phy_config() 337 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_1_hw_phy_config() 338 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_1_hw_phy_config() 364 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_2_hw_phy_config() 365 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_2_hw_phy_config() 366 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_2_hw_phy_config() 386 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_3_hw_phy_config() 387 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_3_hw_phy_config() [all …]
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/linux/drivers/net/phy/ |
A D | nxp-tja11xx.c | 120 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); in tja11xx_enable_reg_write() 125 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_enable_link_control() 145 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup() 278 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_config_init() 666 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST); in tja11xx_cable_test_start() 727 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_get_status()
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A D | mediatek-ge.c | 64 phy_set_bits(phydev, 0x17, BIT(4)); in mt7531_phy_config_init()
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A D | adin.c | 358 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, in adin_set_downshift() 481 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG, in adin_phy_config_intr() 619 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); in adin_config_aneg()
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A D | realtek.c | 328 return phy_set_bits(phydev, MII_CTRL1000, in rtl8211c_config_init() 493 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, in rtl8366rb_config_init()
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A D | icplus.c | 281 ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON); in ip101a_config_init()
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A D | mxl-gpy.c | 444 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); in gpy_set_wol()
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A D | bcm-phy-lib.c | 630 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE); in bcm_phy_enable_jumbo()
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A D | at803x.c | 1505 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); in qca83xx_config_init() 1541 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); in qca83xx_resume()
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A D | broadcom.c | 136 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
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A D | marvell.c | 1193 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init() 1438 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
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A D | micrel.c | 1023 return phy_set_bits(phydev, 0x1e, BIT(9)); in ksz9131_led_errata()
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A D | phy_device.c | 2602 return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_suspend()
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/linux/include/linux/ |
A D | phy.h | 1180 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_set_bits() function
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