Home
last modified time | relevance | path

Searched refs:pipe_mask (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/i915/
A Di915_pci.c160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
181 .pipe_mask = BIT(PIPE_A), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
502 .pipe_mask = 0, /* legal, last one wins */
511 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
606 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
883 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
[all …]
A Dintel_device_info.c329 info->pipe_mask = 0; in intel_device_info_runtime_init()
333 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
340 info->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
344 info->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
348 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
354 info->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
A Di915_irq.h70 u8 pipe_mask);
72 u8 pipe_mask);
A Dintel_device_info.h192 u8 pipe_mask; member
A Di915_drv.h1744 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1746 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
A Di915_irq.c3201 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument
3216 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
3225 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument
3237 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
/linux/drivers/gpu/drm/i915/display/
A Dintel_ddi.c732 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
754 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
757 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
799 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
802 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
811 *pipe_mask); in intel_ddi_get_encoder_pipes()
812 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
840 u8 pipe_mask; in intel_ddi_get_hw_state() local
845 if (is_mst || !pipe_mask) in intel_ddi_get_hw_state()
1961 u8 pipe_mask; in intel_ddi_sanitize_encoder_pll_mapping() local
[all …]
A Dintel_dpll_mgr.c199 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local
208 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
212 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
245 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll() local
268 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
299 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
312 shared_dpll[i].pipe_mask, in intel_find_shared_dpll()
341 if (shared_dpll[id].pipe_mask == 0) in intel_reference_shared_dpll()
347 shared_dpll[id].pipe_mask |= BIT(crtc->pipe); in intel_reference_shared_dpll()
4237 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
[all …]
A Dg4x_hdmi.c594 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
596 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
598 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
A Dintel_dpll_mgr.h245 u8 pipe_mask; member
A Dintel_display_types.h167 u8 pipe_mask; member
1767 INTEL_INFO(i915)->pipe_mask & BIT(pipe) && in intel_pipe_valid()
1782 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); in intel_get_crtc_for_pipe()
A Dg4x_dp.c1391 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1393 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1395 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
A Dintel_lvds.c923 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
925 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
A Dintel_crt.c1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1051 crt->base.pipe_mask = ~0; in intel_crt_init()
A Dvlv_dsi.c1887 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1889 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1891 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
A Dintel_dvo.c524 intel_encoder->pipe_mask = ~0; in intel_dvo_init()
A Dintel_display.c8138 u8 pipe_mask; in verify_single_dpll_state() local
8160 pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state()
8165 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
8172 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_single_dpll_state()
8176 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
8178 pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
8198 u8 pipe_mask = BIT(crtc->pipe); in verify_shared_dpll_state() local
8201 I915_STATE_WARN(pll->active_mask & pipe_mask, in verify_shared_dpll_state()
8204 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask, in verify_shared_dpll_state()
8206 pipe_name(crtc->pipe), pll->state.pipe_mask); in verify_shared_dpll_state()
[all …]
A Dintel_display.h351 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
A Dintel_dp_mst.c915 intel_encoder->pipe_mask = ~0; in intel_dp_create_fake_mst_encoder()
A Dintel_tv.c1962 intel_encoder->pipe_mask = ~0; in intel_tv_init()
A Dicl_dsi.c2027 encoder->pipe_mask = ~0; in icl_dsi_init()
A Dintel_display_debugfs.c1105 pll->state.pipe_mask, pll->active_mask, yesno(pll->on)); in i915_shared_dplls_info()
A Dintel_sdvo.c2997 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_setup()
/linux/drivers/usb/renesas_usbhs/
A Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
/linux/drivers/staging/media/atomisp/pci/
A Dsh_css.c10565 u32 pipe_mask = 0; local
10578 pipe_mask |= (1 << curr_pipe->config.mode);
10582 (((pipe_mask & (1 << IA_CSS_PIPE_MODE_PREVIEW)) ||
10583 (pipe_mask & (1 << IA_CSS_PIPE_MODE_VIDEO))) &&
10584 (pipe_mask & (1 << IA_CSS_PIPE_MODE_CAPTURE)) &&

Completed in 137 milliseconds