| /linux/Documentation/devicetree/bindings/clock/ |
| A D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1-clk";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
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| A D | qoriq-clock.txt | 167 pll1: pll1@820 {
172 clock-output-names = "pll1", "pll1-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| A D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
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| A D | allwinner,sun4i-a10-cpu-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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| A D | renesas,cpg-clocks.yaml | 75 - const: pll1
201 - const: pll1
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| A D | imx28-clock.yaml | 21 pll1 2
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| A D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
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| /linux/drivers/gpu/drm/hisilicon/hibmc/ |
| A D | hibmc_drm_de.c | 284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
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| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| A D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
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| /linux/Documentation/devicetree/bindings/clock/st/ |
| A D | st,clkgen-pll.txt | 15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
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| /linux/drivers/gpu/drm/tegra/ |
| A D | hdmi.c | 37 u32 pll1; member
132 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
147 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
165 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
179 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
228 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
247 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
266 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
307 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
[all …]
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| A D | sor.c | 366 unsigned int pll1; member
769 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
771 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
900 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
917 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
3292 .pll1 = 0x18,
3464 .pll1 = 0x18,
3525 .pll1 = 0x164,
[all …]
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| /linux/sound/soc/codecs/ |
| A D | tscs454.c | 131 struct pll pll1; member
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
710 bool pll1; in pll_power_event() local
716 pll1 = true; in pll_power_event()
718 pll1 = false; in pll_power_event()
741 pll1 ? 1 : 2, in pll_power_event()
[all …]
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| /linux/arch/arm/boot/dts/ |
| A D | stih407-clock.dtsi | 109 clk_s_c0_pll1: clk-s-c0-pll1 {
111 compatible = "st,clkgen-pll1-c0";
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| A D | stih410-clock.dtsi | 109 clk_s_c0_pll1: clk-s-c0-pll1 {
111 compatible = "st,clkgen-pll1-c0";
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| A D | stih418-clock.dtsi | 110 clk_s_c0_pll1: clk-s-c0-pll1 {
112 compatible = "st,clkgen-pll1-c0";
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| A D | dra72x.dtsi | 72 reg-names = "dss", "pll1_clkctrl", "pll1";
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| A D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
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| /linux/arch/arm/mach-davinci/ |
| A D | dm646x.c | 653 void __iomem *pll1, *psc; in dm646x_init_time() local
660 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm646x_init_time()
661 dm646x_pll1_init(NULL, pll1, NULL); in dm646x_init_time()
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| A D | dm644x.c | 670 void __iomem *pll1, *psc; in dm644x_init_time() local
676 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm644x_init_time()
677 dm644x_pll1_init(NULL, pll1, NULL); in dm644x_init_time()
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| A D | dm355.c | 734 void __iomem *pll1, *psc; in dm355_init_time() local
740 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); in dm355_init_time()
741 dm355_pll1_init(NULL, pll1, NULL); in dm355_init_time()
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| /linux/drivers/clk/mxs/ |
| A D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
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| /linux/Documentation/devicetree/bindings/display/ti/ |
| A D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
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| /linux/Documentation/translations/zh_CN/core-api/ |
| A D | printk-formats.rst | 524 %pC pll1
525 %pCn pll1
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