Home
last modified time | relevance | path

Searched refs:pll_mode (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/ptp/
A Dptp_idt82p33.h61 enum pll_mode { enum
124 enum pll_mode pll_mode; member
A Dptp_idt82p33.c186 enum pll_mode mode) in idt82p33_dpll_set_mode()
192 if (channel->pll_mode == mode) in idt82p33_dpll_set_mode()
209 channel->pll_mode = dpll_mode; in idt82p33_dpll_set_mode()
A Dptp_clockmatrix.c1383 enum pll_mode *mode) in idtcm_get_pll_mode()
1401 enum pll_mode mode) in idtcm_set_pll_mode()
1642 enum pll_mode mode) in initialize_operating_mode_with_pll_mode()
1671 enum pll_mode mode = PLL_MODE_DISABLED; in initialize_dco_operating_mode()
/linux/drivers/clk/axis/
A Dclk-artpec6.c42 u32 pll_mode, pll_m, pll_n; in of_artpec6_clkctrl_setup() local
65 pll_mode = (readl(clkdata->syscon_base) >> 6) & 3; in of_artpec6_clkctrl_setup()
66 switch (pll_mode) { in of_artpec6_clkctrl_setup()
/linux/drivers/clk/zynqmp/
A Dpll.c33 enum pll_mode { enum
49 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) in zynqmp_pll_get_mode()
144 enum pll_mode mode; in zynqmp_pll_recalc_rate()
/linux/include/linux/mfd/
A Didt82p33_reg.h70 enum pll_mode { enum
A Didt8a340_reg.h659 enum pll_mode { enum
/linux/drivers/clk/pistachio/
A Dclk-pll.c66 enum pll_mode { enum
105 static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw) in pll_frac_get_mode()
114 static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode) in pll_frac_set_mode()
/linux/drivers/net/wireless/rsi/
A Drsi_main.h224 u8 pll_mode; member
A Drsi_91x_mgmt.c291 common->w9116_features.pll_mode = 0x0; in rsi_set_default_parameters()
1706 w9116_features->pll_mode = common->w9116_features.pll_mode; in rsi_send_w9116_features()
A Drsi_mgmt.h673 u8 pll_mode; member
/linux/sound/soc/codecs/
A Dcs42l42.c566 u8 pll_mode; member
702 pll_ratio_table[i].pll_mode in cs42l42_pll_config()
A Dcs43130.c185 u8 pll_mode; member
278 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); in cs43130_pll_config()
/linux/drivers/video/fbdev/
A Dw100fb.h680 u32 pll_mode : 1; member
A Dw100fb.c1247 w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */ in w100_pwm_setup()
/linux/Documentation/driver-api/media/drivers/ccs/
A Dccs-regs.asc214 pll_mode 0x0310 8

Completed in 41 milliseconds