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Searched refs:pll_value (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/staging/sm750fb/
A Dddk750_chip.h42 struct pll_value { struct
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
98 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL);
A Dddk750_chip.c58 struct pll_value pll; in set_chip_clock()
313 struct pll_value *pll) in sm750_calc_pll_value()
385 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL) in sm750_format_pll_reg()
A Dddk750_mode.c79 struct pll_value *pll) in programModeRegisters()
212 struct pll_value pll; in ddk750_setModeTiming()
/linux/arch/m68k/q40/
A Dconfig.c262 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
264 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
279 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
/linux/drivers/video/fbdev/geode/
A Dvideo_cs5530.c25 u32 pll_value; member
76 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()
84 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
/linux/drivers/mmc/host/
A Dsdhci-pci-gli.c177 u32 pll_value; in gli_set_9750() local
187 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
209 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; in gli_set_9750()
210 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; in gli_set_9750()
211 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()
213 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()
237 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
/linux/include/uapi/linux/
A Drtc.h62 int pll_value; /* get/set correction value */ member

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