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Searched refs:pllvals (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/nouveau/dispnv04/
A Dhw.c140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
153 pllvals->M1 &= 0xf; /* only 4 bits */ in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
165 struct nvkm_pll_vals *pllvals) in nouveau_hw_get_pllvals() argument
200 pllvals->refclk = pll_lim.refclk; in nouveau_hw_get_pllvals()
[all …]
A Dhw.h44 struct nvkm_pll_vals *pllvals);
45 int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
A Ddisp.h42 struct nvkm_pll_vals pllvals; member
A Ddfp.c605 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals); in nv04_dfp_restore()
A Dcrtc.c126 struct nvkm_pll_vals *pv = &regp->pllvals; in nv_crtc_calc_state_ext()

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