Searched refs:rFPGA0_XA_HSSIParameter1 (Results 1 – 10 of 10) sorted by relevance
10 #define rFPGA0_XA_HSSIParameter1 0x820 macro
608 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
181 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8)); in phy_RFSerialRead()429 …pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1… in phy_InitBBRFRegisterDefinition()
706 ODM_SetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); in _PHY_PIModeSwitch()828 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)ODM_GetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, BIT(8)); in phy_IQCalibrate_8188E()
53 #define rFPGA0_XA_HSSIParameter1 0x820 macro
417 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in _rtl92e_init_bb_rf_reg_def()
93 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
102 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
64 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
133 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()
Completed in 32 milliseconds