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Searched refs:rFPGA0_XA_HSSIParameter1 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/staging/rtl8192u/
A Dr819xU_phyreg.h10 #define rFPGA0_XA_HSSIParameter1 0x820 macro
A Dr819xU_phy.c608 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in rtl8192_InitBBRFRegDef()
/linux/drivers/staging/r8188eu/hal/
A Drtl8188e_phycfg.c181 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8)); in phy_RFSerialRead()
429 …pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1… in phy_InitBBRFRegisterDefinition()
A DHalPhyRf_8188e.c706 ODM_SetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); in _PHY_PIModeSwitch()
828 dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)ODM_GetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, BIT(8)); in phy_IQCalibrate_8188E()
/linux/drivers/staging/rtl8192e/rtl8192e/
A Dr8192E_phyreg.h53 #define rFPGA0_XA_HSSIParameter1 0x820 macro
A Dr8192E_phy.c417 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; in _rtl92e_init_bb_rf_reg_def()
/linux/drivers/staging/rtl8712/
A Drtl871x_mp_phy_regdef.h93 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
/linux/drivers/staging/rtl8723bs/include/
A DHal8192CPhyReg.h102 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
/linux/drivers/staging/r8188eu/include/
A DHal8188EPhyReg.h64 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ macro
/linux/drivers/staging/rtl8723bs/hal/
A Drtl8723b_phycfg.c133 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); in phy_RFSerialRead_8723B()

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