Searched refs:rG0 (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/powerpc/crypto/ |
| A D | aes-spe-modes.S | 67 stw rG0,112(r1); /* save 32 bit registers */ \
74 lwz rG0,112(r1); /* restore 32 bit registers */ \
516 ENDIAN_SWAP(rG0, rG1, rI0, rI1)
543 GF128_MUL(rG0, rG1, rG2, rG3, rW0)
544 ENDIAN_SWAP(rI0, rI1, rG0, rG1)
586 ENDIAN_SWAP(rG0, rG1, rI0, rI1)
613 GF128_MUL(rG0, rG1, rG2, rG3, rW0)
614 ENDIAN_SWAP(rI0, rI1, rG0, rG1)
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| A D | aes-spe-regs.h | 34 #define rG0 r28 /* endian reversed tweak (XTS mode) */ macro
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