Searched refs:set_wptr (Results 1 – 25 of 32) sorted by relevance
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| /linux/drivers/gpu/drm/radeon/ |
| A D | radeon_asic.c | 195 .set_wptr = &r100_gfx_set_wptr,
345 .set_wptr = &r100_gfx_set_wptr,
359 .set_wptr = &r100_gfx_set_wptr,
916 .set_wptr = &r600_gfx_set_wptr,
929 .set_wptr = &r600_dma_set_wptr,
1014 .set_wptr = &uvd_v1_0_set_wptr,
1213 .set_wptr = &uvd_v1_0_set_wptr,
1320 .set_wptr = &r600_gfx_set_wptr,
1333 .set_wptr = &r600_dma_set_wptr,
1658 .set_wptr = &uvd_v1_0_set_wptr,
[all …]
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| A D | radeon.h | 1844 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2757 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_ring.h | 155 void (*set_wptr)(struct amdgpu_ring *ring); member
262 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
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| A D | jpeg_v2_5.c | 628 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
658 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
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| A D | vce_v3_0.c | 928 .set_wptr = vce_v3_0_ring_set_wptr,
952 .set_wptr = vce_v3_0_ring_set_wptr,
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| A D | uvd_v6_0.c | 1551 .set_wptr = uvd_v6_0_ring_set_wptr,
1577 .set_wptr = uvd_v6_0_ring_set_wptr,
1606 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
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| A D | vcn_v2_5.c | 1518 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1548 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1648 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1678 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
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| A D | jpeg_v3_0.c | 560 .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
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| A D | vce_v2_0.c | 641 .set_wptr = vce_v2_0_ring_set_wptr,
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| A D | sdma_v4_0.c | 2421 .set_wptr = sdma_v4_0_ring_set_wptr,
2457 .set_wptr = sdma_v4_0_ring_set_wptr,
2489 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2521 .set_wptr = sdma_v4_0_page_ring_set_wptr,
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| A D | uvd_v3_1.c | 186 .set_wptr = uvd_v3_1_ring_set_wptr,
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| A D | uvd_v4_2.c | 775 .set_wptr = uvd_v4_2_ring_set_wptr,
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| A D | jpeg_v1_0.c | 555 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
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| A D | jpeg_v2_0.c | 764 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
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| A D | uvd_v5_0.c | 883 .set_wptr = uvd_v5_0_ring_set_wptr,
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| A D | vcn_v3_0.c | 1786 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1941 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
2042 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
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| A D | si_dma.c | 731 .set_wptr = si_dma_ring_set_wptr,
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| A D | uvd_v7_0.c | 1806 .set_wptr = uvd_v7_0_ring_set_wptr,
1839 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
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| A D | vcn_v1_0.c | 1909 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1943 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
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| A D | vcn_v2_0.c | 2009 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2040 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
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| A D | mes_v10_1.c | 81 .set_wptr = mes_v10_1_ring_set_wptr,
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| A D | sdma_v2_4.c | 1147 .set_wptr = sdma_v2_4_ring_set_wptr,
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| A D | cik_sdma.c | 1258 .set_wptr = cik_sdma_ring_set_wptr,
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| A D | vce_v4_0.c | 1109 .set_wptr = vce_v4_0_ring_set_wptr,
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| A D | sdma_v3_0.c | 1585 .set_wptr = sdma_v3_0_ring_set_wptr,
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Completed in 71 milliseconds
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