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Searched refs:socfpgaclk (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/clk/socfpga/
A Dclk-gate-s10.c27 if (socfpgaclk->fixed_div) { in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
44 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_dbg_clk_recalc_rate()
58 if (socfpgaclk->bypass_reg) { in socfpga_gate_get_parent()
61 socfpgaclk->bypass_shift); in socfpga_gate_get_parent()
88 if (socfpgaclk->bypass_reg) { in socfpga_agilex_gate_get_parent()
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A Dclk-periph-s10.c23 unsigned long shift = socfpgaclk->shift; in n5x_clk_peri_c_clk_recalc_rate()
26 val = readl(socfpgaclk->hw.reg); in n5x_clk_peri_c_clk_recalc_rate()
40 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
53 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
54 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
56 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
70 if (socfpgaclk->bypass_reg) { in clk_periclk_get_parent()
71 mask = (0x1 << socfpgaclk->bypass_shift); in clk_periclk_get_parent()
73 socfpgaclk->bypass_shift); in clk_periclk_get_parent()
78 if (socfpgaclk->hw.reg) { in clk_periclk_get_parent()
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A Dclk-pll-s10.c48 reg = readl(socfpgaclk->hw.reg + 0x8); in n5x_clk_pll_recalc_rate()
69 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()
75 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()
92 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
99 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
112 div = ((readl(socfpgaclk->hw.reg) & in clk_boot_clk_recalc_rate()
125 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
135 pll_src = readl(socfpgaclk->hw.reg); in clk_boot_get_parent()
146 reg = readl(socfpgaclk->hw.reg); in clk_pll_prepare()
148 writel(reg, socfpgaclk->hw.reg); in clk_pll_prepare()
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A Dclk-gate-a10.c24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_gate_clk_recalc_rate() local
27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
79 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) in socfpga_clk_prepare()
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A Dclk-periph-a10.c23 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
26 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
27 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
30 div &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
33 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_periclk_recalc_rate()
41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_get_parent() local
45 clk_src = readl(socfpgaclk->hw.reg); in clk_periclk_get_parent()
A Dclk-gate.c93 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_recalc_rate() local
96 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()
97 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()
98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
100 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_clk_recalc_rate()
102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
113 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); in socfpga_clk_prepare() local
119 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
127 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
A Dclk-periph.c20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); in clk_periclk_recalc_rate() local
23 if (socfpgaclk->fixed_div) { in clk_periclk_recalc_rate()
24 div = socfpgaclk->fixed_div; in clk_periclk_recalc_rate()
26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
28 val &= GENMASK(socfpgaclk->width - 1, 0); in clk_periclk_recalc_rate()
31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); in clk_periclk_recalc_rate()
A Dclk-pll-a10.c37 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
A Dclk-pll.c41 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_recalc_rate() local
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
61 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); in clk_pll_get_parent() local
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()

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