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Searched refs:tf_mask (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
278 reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
297 reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
470 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp1_program_input_csc()
472 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp1_program_input_csc()
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A Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
501 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control()
556 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument
566 dpp->tf_mask = tf_mask; in dpp1_construct()
A Ddcn10_dpp_dscl.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
409 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
A Ddcn10_resource.c426 static const struct dcn_dpp_mask tf_mask = { variable
652 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
A Ddcn10_dpp.h1357 const struct dcn_dpp_mask *tf_mask; member
1519 const struct dcn_dpp_mask *tf_mask);
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dpp_cm.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
180 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
182 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
185 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
189 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
194 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
196 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
198 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
202 reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
348 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
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A Ddcn30_dpp.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
104 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc()
644 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
648 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
653 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
655 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
657 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
661 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1485 const struct dcn3_dpp_mask *tf_mask) in dpp3_construct() argument
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A Ddcn30_dpp.h563 const struct dcn3_dpp_mask *tf_mask; member
582 const struct dcn3_dpp_mask *tf_mask);
A Ddcn30_resource.c558 static const struct dcn3_dpp_mask tf_mask = { variable
895 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn30_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp_cm.c47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc()
287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc()
363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
374 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
376 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
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A Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
420 const struct dcn2_dpp_mask *tf_mask) in dpp2_construct() argument
430 dpp->tf_mask = tf_mask; in dpp2_construct()
A Ddcn20_dpp.h683 const struct dcn2_dpp_mask *tf_mask; member
773 const struct dcn2_dpp_mask *tf_mask);
A Ddcn20_resource.c791 static const struct dcn2_dpp_mask tf_mask = { variable
1117 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_dpp.h62 const struct dcn201_dpp_mask *tf_mask; member
81 const struct dcn201_dpp_mask *tf_mask);
A Ddcn201_dpp.c42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
295 const struct dcn201_dpp_mask *tf_mask) in dpp201_construct() argument
305 dpp->tf_mask = tf_mask; in dpp201_construct()
A Ddcn201_resource.c479 static const struct dcn201_dpp_mask tf_mask = { variable
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c414 static const struct dcn3_dpp_mask tf_mask = { variable
737 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c668 static const struct dcn3_dpp_mask tf_mask = { variable
679 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c627 static const struct dcn3_dpp_mask tf_mask = { variable
638 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c672 static const struct dcn2_dpp_mask tf_mask = { variable
741 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c631 static const struct dcn3_dpp_mask tf_mask = { variable
1071 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()

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