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Searched refs:tiling_flags (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/gpu/drm/radeon/
A Dradeon_object.c545 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
550 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
566 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
605 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
627 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
635 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
680 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
687 uint32_t *tiling_flags, in radeon_bo_get_tiling_flags() argument
692 if (tiling_flags) in radeon_bo_get_tiling_flags()
693 *tiling_flags = bo->tiling_flags; in radeon_bo_get_tiling_flags()
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A Dradeon_fb.c135 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
162 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
167 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
170 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
177 if (tiling_flags) { in radeonfb_create_pinned_object()
179 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
A Dr300.c718 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
720 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
722 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
787 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
789 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
791 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
872 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
874 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
876 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
A Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
A Dradeon_object.h158 u32 tiling_flags, u32 pitch);
160 u32 *tiling_flags, u32 *pitch);
A Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
A Devergreen_cs.c92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
94 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
96 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1184 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1445 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1448 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1473 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1476 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
2362 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
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A Datombios_crtc.c1154 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1191 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1274 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1275 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1348 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1475 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1510 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1586 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1588 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1591 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
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A Dr100.c1290 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1632 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1634 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3090 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3100 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3107 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()
3109 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3112 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3114 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3118 if (tiling_flags & RADEON_TILING_SWAP_16BIT) in r100_set_surface_reg()
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A Dr600_cs.c1043 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1142 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1145 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1476 u32 tiling_flags) in r600_check_texture_resource() argument
1498 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1500 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1969 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1971 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1987 reloc->tiling_flags); in r600_packet3_check()
A Dradeon_gem.c584 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
605 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
A Dradeon_vm.c147 list[0].tiling_flags = 0; in radeon_vm_get_bos()
159 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
A Dradeon_display.c491 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
537 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
545 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
A Dradeon.h356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
465 uint32_t tiling_flags; member
496 u32 tiling_flags; member
1965 uint32_t tiling_flags, uint32_t pitch,
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_display.c159 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
213 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
683 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
788 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
846 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) in check_tiling_flags_gfx6()
1031 uint64_t *tiling_flags, bool *tmz_surface) in amdgpu_display_get_fb_info() argument
1037 *tiling_flags = 0; in amdgpu_display_get_fb_info()
1052 if (tiling_flags) in amdgpu_display_get_fb_info()
1053 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in amdgpu_display_get_fb_info()
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A Damdgpu_fb.c129 u32 tiling_flags = 0, domain; in amdgpufb_create_pinned_object() local
157 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
163 if (tiling_flags) { in amdgpufb_create_pinned_object()
165 tiling_flags); in amdgpufb_create_pinned_object()
A Damdgpu_object.h116 u64 tiling_flags; member
309 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
310 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
A Damdgpu_object.c1073 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1080 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1084 ubo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1096 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1104 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1105 *tiling_flags = ubo->tiling_flags; in amdgpu_bo_get_tiling_flags()
A Ddce_v8_0.c1787 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
A Ddce_v6_0.c1817 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1853 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1936 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1939 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1940 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1941 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1942 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1943 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1951 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1955 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
A Ddce_v10_0.c1858 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1895 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1898 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1988 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1992 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1994 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1995 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2008 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
A Ddce_v11_0.c1900 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
A Damdgpu_mode.h305 uint64_t tiling_flags; member
/linux/include/uapi/drm/
A Dradeon_drm.h858 __u32 tiling_flags; member
864 __u32 tiling_flags; member
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c4701 uint64_t tiling_flags) in fill_gfx8_tiling_info_from_flags() argument
4707 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_gfx8_tiling_info_from_flags()
4708 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_gfx8_tiling_info_from_flags()
4729 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_gfx8_tiling_info_from_flags()
5265 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
5424 const uint64_t tiling_flags, in fill_dc_plane_info_and_addr() argument
5522 plane_info->rotation, tiling_flags, in fill_dc_plane_info_and_addr()
5560 afb->tiling_flags, in fill_dc_plane_attributes()
7499 afb->tiling_flags, in dm_plane_helper_prepare_fb()
9089 afb->tiling_flags, in amdgpu_dm_commit_planes()
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