Home
last modified time | relevance | path

Searched refs:tiling_info (Results 1 – 25 of 27) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c141 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
142 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
143 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
144 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
146 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
148 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
150 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
161 plane_state->tiling_info.gfx8.pipe_config, in pre_surface_trace()
162 plane_state->tiling_info.gfx8.array_mode, in pre_surface_trace()
[all …]
A Ddc_hw_sequencer.c418 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
A Ddc.c2169 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, in get_plane_info_update_type()
2177 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
2500 surface->tiling_info = in copy_surface_update_to_plane()
2501 srf_update->plane_info->tiling_info; in copy_surface_update_to_plane()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_mem_input.c101 union dc_tiling_info *tiling_info) in get_mi_tiling() argument
103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
136 union dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
141 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
633 union dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
642 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
654 union dc_tiling_info *tiling_info, in dce60_mi_program_surface_config() argument
663 program_tiling(dce_mi, tiling_info); in dce60_mi_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_mem_input_v.c528 union dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
546 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
568 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
572 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
573 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
641 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
650 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
A Ddce110_hw_sequencer.c2099 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2792 &plane_state->tiling_info,
2804 &plane_state->tiling_info,
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dmem_input.h142 union dc_tiling_info *tiling_info,
156 union dc_tiling_info *tiling_info,
A Dhubp.h118 union dc_tiling_info *tiling_info,
132 union dc_tiling_info *tiling_info,
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_hubp.c45 union dc_tiling_info *tiling_info, in hubp201_program_surface_config() argument
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_hw_sequencer.c105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
319 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
331 &plane_state->tiling_info, in dce60_program_front_end_for_pipe()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm.c4715 tiling_info->gfx8.array_mode = in fill_gfx8_tiling_info_from_flags()
4721 tiling_info->gfx8.tile_mode = in fill_gfx8_tiling_info_from_flags()
4728 tiling_info->gfx8.pipe_config = in fill_gfx8_tiling_info_from_flags()
4736 tiling_info->gfx9.num_pipes = in fill_gfx9_tiling_info_from_device()
4738 tiling_info->gfx9.num_banks = in fill_gfx9_tiling_info_from_device()
4740 tiling_info->gfx9.pipe_interleave = in fill_gfx9_tiling_info_from_device()
4746 tiling_info->gfx9.num_rb_per_se = in fill_gfx9_tiling_info_from_device()
5276 memset(tiling_info, 0, sizeof(*tiling_info)); in fill_plane_buffer_attributes()
5330 tiling_info, dcc, in fill_plane_buffer_attributes()
5523 &plane_info->tiling_info, in fill_dc_plane_info_and_addr()
[all …]
A Damdgpu_dm_trace.h448 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_hubp.c402 union dc_tiling_info *tiling_info, in hubp3_program_surface_config() argument
412 hubp3_program_tiling(hubp2, tiling_info, format); in hubp3_program_surface_config()
A Ddcn30_hubp.h267 union dc_tiling_info *tiling_info,
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc.h963 union dc_tiling_info tiling_info; member
1018 union dc_tiling_info tiling_info; member
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_gem.c570 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
580 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_hubp.h323 union dc_tiling_info *tiling_info,
A Ddcn20_hubp.c538 union dc_tiling_info *tiling_info, in hubp2_program_surface_config() argument
548 hubp2_program_tiling(hubp2, tiling_info, format); in hubp2_program_surface_config()
A Ddcn20_resource.c2342 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
2343 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
3378 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn20_patch_unknown_plane_state()
A Ddcn20_hwseq.c1549 &plane_state->tiling_info, in dcn20_update_dchubp_dpp()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hubp.c538 union dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
546 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
A Ddcn10_hubp.h702 union dc_tiling_info *tiling_info,
A Ddcn10_resource.c1279 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
/linux/include/uapi/drm/
A Damdgpu_drm.h380 __u64 tiling_info; member
/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1029 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()

Completed in 85 milliseconds

12