| /linux/arch/arm64/include/asm/ |
| A D | mmu_context.h | 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0() local
45 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
198 u64 ttbr; in update_saved_ttbr0() local
204 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
206 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
208 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| A D | assembler.h | 587 .macro offset_ttbr1, ttbr, tmp
592 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
602 .macro restore_ttbr1, ttbr
604 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
615 .macro phys_to_ttbr, ttbr, phys
617 orr \ttbr, \phys, \phys, lsr #46
618 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
620 mov \ttbr, \phys
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| A D | uaccess.h | 80 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
83 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
84 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
86 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
89 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| /linux/drivers/gpu/drm/msm/ |
| A D | msm_iommu.c | 24 phys_addr_t ttbr; member
101 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params() argument
110 if (ttbr) in msm_iommu_pagetable_params()
111 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
210 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
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| A D | msm_mmu.h | 59 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /linux/arch/arm/include/asm/ |
| A D | proc-fns.h | 160 u64 ttbr; \
162 : "=r" (ttbr)); \
163 ttbr; \
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| /linux/include/linux/ |
| A D | io-pgtable.h | 99 u64 ttbr; member
125 u32 ttbr; member
137 u64 ttbr[4]; member
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| /linux/drivers/iommu/arm/arm-smmu/ |
| A D | arm-smmu-qcom.c | 139 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
151 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
152 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
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| A D | arm-smmu.c | 500 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
501 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
503 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
505 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
509 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
511 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
514 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
589 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
590 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
592 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
[all …]
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| A D | arm-smmu.h | 354 u64 ttbr[2]; member
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| A D | qcom_iommu.c | 278 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | in qcom_iommu_init_domain()
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| /linux/drivers/iommu/ |
| A D | ipmmu-vmsa.c | 371 u64 ttbr; in ipmmu_domain_setup_context() local
375 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
376 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
377 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| A D | mtk_iommu.c | 480 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
982 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
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| A D | io-pgtable-arm.c | 920 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
1145 cfg->apple_dart_cfg.ttbr[i] = in apple_dart_alloc_pgtable()
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| A D | apple-dart.c | 393 pgtbl_cfg->apple_dart_cfg.ttbr[i]); in apple_dart_setup_translation()
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| A D | msm_iommu.c | 274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
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| A D | io-pgtable-arm-v7s.c | 849 cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | in arm_v7s_alloc_pgtable()
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| /linux/drivers/gpu/drm/msm/adreno/ |
| A D | a6xx_gpu.c | 105 phys_addr_t ttbr; in a6xx_set_pagetable() local
112 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
117 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
120 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
131 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
132 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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| /linux/drivers/iommu/arm/arm-smmu-v3/ |
| A D | arm-smmu-v3-sva.c | 150 cd->ttbr = virt_to_phys(mm->pgd); in arm_smmu_alloc_shared_cd()
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| A D | arm-smmu-v3.h | 575 u64 ttbr; member
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| A D | arm-smmu-v3.c | 1080 cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); in arm_smmu_write_ctx_desc()
2096 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_domain_finalise_s1()
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