/linux/drivers/gpu/drm/i915/gvt/ |
A D | display.c | 377 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change() 379 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= in emulate_monitor_status_change() 381 vgpu_vreg_t(vgpu, LCPLL1_CTL) = in emulate_monitor_status_change() 398 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change() 400 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change() 402 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change() 424 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change() 426 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change() 428 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change() 450 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change() [all …]
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A D | mmio.c | 249 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; in intel_vgpu_reset_mmio() 252 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; in intel_vgpu_reset_mmio() 255 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in intel_vgpu_reset_mmio() 258 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio() 268 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio() 270 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio() 273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio() 275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio() 278 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in intel_vgpu_reset_mmio() 280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in intel_vgpu_reset_mmio() [all …]
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A D | fb_decoder.c | 213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane() 266 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane() 270 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); in intel_vgpu_decode_primary_plane() 344 val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); in intel_vgpu_decode_cursor_plane() 381 val = vgpu_vreg_t(vgpu, CURPOS(pipe)); in intel_vgpu_decode_cursor_plane() 387 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane() 423 val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); in intel_vgpu_decode_sprite_plane() 485 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & in intel_vgpu_decode_sprite_plane() 488 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); in intel_vgpu_decode_sprite_plane() 496 val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); in intel_vgpu_decode_sprite_plane() [all …]
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A D | vgpu.c | 43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; in populate_pvinfo_page() 44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; in populate_pvinfo_page() 45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; in populate_pvinfo_page() 46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page() 48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; in populate_pvinfo_page() 50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; in populate_pvinfo_page() 52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = in populate_pvinfo_page() 54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = in populate_pvinfo_page() 56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = in populate_pvinfo_page() 63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX; in populate_pvinfo_page() [all …]
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A D | edid.c | 128 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller() 130 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller() 162 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus0_mmio_write() 163 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; in gmbus0_mmio_write() 169 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; in gmbus0_mmio_write() 171 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in gmbus0_mmio_write() 198 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; in gmbus1_mmio_write() 199 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; in gmbus1_mmio_write() 247 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus1_mmio_write() 259 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; in gmbus1_mmio_write() [all …]
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A D | mmio_context.c | 256 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit() 389 vgpu_vreg_t(vgpu, reg) = 0; in handle_tlb_pending_event() 423 old_v = vgpu_vreg_t(pre, offset); in switch_mocs() 427 new_v = vgpu_vreg_t(next, offset); in switch_mocs() 441 old_v = vgpu_vreg_t(pre, l3_offset); in switch_mocs() 445 new_v = vgpu_vreg_t(next, l3_offset); in switch_mocs() 496 vgpu_vreg_t(pre, mmio->reg) = in switch_mmio() 499 vgpu_vreg_t(pre, mmio->reg) &= in switch_mmio() 501 old_v = vgpu_vreg_t(pre, mmio->reg); in switch_mmio() 520 new_v = vgpu_vreg_t(next, mmio->reg) | in switch_mmio() [all …]
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A D | handlers.c | 349 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write() 381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write() 387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write() 605 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & in skl_vgpu_get_dp_bitrate() 615 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & in skl_vgpu_get_dp_bitrate() 801 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) in ddi_buf_ctl_mmio_write() 934 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= in update_fdi_rx_iir_status() 955 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); in dp_tp_ctl_mmio_write() 1016 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; in pri_surf_mmio_write() 1058 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; in reg50080_mmio_write() [all …]
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A D | cmd_parser.c | 1394 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); in gen8_check_mi_display_flip() 1395 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip() 1398 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & in gen8_check_mi_display_flip() 1400 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip() 1419 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), in gen8_update_plane_mmio_from_mi_display_flip() 1422 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), in gen8_update_plane_mmio_from_mi_display_flip() 1424 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip() 1427 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), in gen8_update_plane_mmio_from_mi_display_flip() 1429 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip() 1434 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; in gen8_update_plane_mmio_from_mi_display_flip()
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A D | scheduler.c | 651 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx() 969 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; in update_guest_context() 970 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; in update_guest_context()
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A D | gvt.h | 451 #define vgpu_vreg_t(vgpu, reg) \ macro
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A D | gtt.c | 1059 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & in vgpu_ips_enabled()
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