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/optee_os/core/drivers/clk/
A Dclk-stm32mp15.c718 uint32_t cfgr2 = 0; in stm32mp1_read_pll_freq() local
724 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()
725 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; in stm32mp1_read_pll_freq()

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