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Searched refs:io_read32 (Results 1 – 25 of 92) sorted by relevance

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/optee_os/core/drivers/
A Dtzc380.c57 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
67 return io_read32(base + ACTION_OFF); in tzc_read_action()
84 return io_read32(base + REGION_ATTRIBUTES_OFF(region)); in tzc_read_region_attributes()
146 io_read32(base + FAIL_ADDRESS_LOW_OFF)); in tzc_fail_dump()
148 io_read32(base + FAIL_ADDRESS_HIGH_OFF)); in tzc_fail_dump()
150 EMSG("Fail Id 0x%" PRIx32, io_read32(base + FAIL_ID)); in tzc_fail_dump()
305 check = io_read32(tzc.base + LOCKDOWN_RANGE_OFF); in tzc_regions_lockdown()
311 check = io_read32(tzc.base + LOCKDOWN_SELECT_OFF); in tzc_regions_lockdown()
338 io_read32(tzc.base + SECURITY_INV_EN_OFF)); in tzc_dump_state()
355 io_read32(tzc.base + LOCKDOWN_SELECT_OFF)); in tzc_dump_state()
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A Ddra7_rng.c91 while (!(io_read32(rng + RNG_STATUS) & RNG_READY)) { in hw_get_random_byte()
93 if (io_read32(rng + RNG_STATUS) & SHUTDOWN_OFLO) { in hw_get_random_byte()
94 uint32_t alarm = io_read32(rng + RNG_ALARMSTOP); in hw_get_random_byte()
95 uint32_t tune = io_read32(rng + RNG_FRODETUNE); in hw_get_random_byte()
111 random.val[0] = io_read32(rng + RNG_OUTPUT_L); in hw_get_random_byte()
112 random.val[1] = io_read32(rng + RNG_OUTPUT_H); in hw_get_random_byte()
137 while (io_read32(rng + RNG_SOFT_RESET_REG) & RNG_SOFT_RESET) in dra7_rng_init()
A Dtzc400.c84 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
89 return io_read32(base + GATE_KEEPER_OFF); in tzc_read_gate_keeper()
104 return io_read32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_base_low()
126 return io_read32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_low()
137 return io_read32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region)); in tzc_read_region_top_high()
387 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in write_not_read()
393 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in nonsecure_not_secure()
399 return io_read32(tzc.base + FAIL_CONTROL(filter)) & in priv_not_unpriv()
406 uint32_t status = io_read32(tzc.base + INT_STATUS); in dump_fail_filter()
423 io_read32(tzc.base + FAIL_ADDRESS_LOW(filter))); in dump_fail_filter()
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A Dimx_uart.c99 while (!(io_read32(base + UTS) & UTS_TXEMPTY)) in imx_uart_flush()
100 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_flush()
108 while (io_read32(base + UTS) & UTS_RXEMPTY) in imx_uart_getchar()
111 return (io_read32(base + URXD) & URXD_RX_DATA); in imx_uart_getchar()
119 while (io_read32(base + UTS) & UTS_TXFULL) in imx_uart_putc()
120 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) in imx_uart_putc()
A Dgic.c108 old_ctlr = io_read32(gicc_base + GICC_CTLR); in probe_max_it()
116 old_reg = io_read32(gicd_base + GICD_ISENABLER(i)); in probe_max_it()
118 reg = io_read32(gicd_base + GICD_ISENABLER(i)); in probe_max_it()
281 assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); in gic_it_set_cpu_mask()
284 target = io_read32(itargetsr); in gic_it_set_cpu_mask()
290 DMSG("cpu_mask: 0x%x", io_read32(itargetsr)); in gic_it_set_cpu_mask()
299 assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); in gic_it_set_prio()
314 assert(!(io_read32(base + GICD_IGROUPR(idx)) & mask)); in gic_it_enable()
365 return io_read32(gd->gicc_base + GICC_IAR); in gic_read_iar()
410 DMSG("GICC_CTLR: 0x%x", io_read32(gd->gicc_base + GICC_CTLR)); in gic_dump_state()
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A Damlogic_uart.c37 while (!(io_read32(base + AML_UART_STATUS) & AML_UART_TX_EMPTY)) in amlogic_uart_flush()
45 if (io_read32(base + AML_UART_STATUS) & AML_UART_RX_EMPTY) in amlogic_uart_getchar()
48 return io_read32(base + AML_UART_RFIFO) & 0xff; in amlogic_uart_getchar()
55 while (io_read32(base + AML_UART_STATUS) & AML_UART_TX_FULL) in amlogic_uart_putc()
A Datmel_uart.c65 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) in atmel_uart_flush()
73 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) in atmel_uart_getchar()
76 return io_read32(base + ATMEL_UART_RHR); in atmel_uart_getchar()
83 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) in atmel_uart_putc()
A Dstm32_rng.c65 if (io_read32(rng_base + RNG_SR) & (RNG_SR_SECS | RNG_SR_SEIS)) { in conceal_seed_error()
71 (void)io_read32(rng_base + RNG_DR); in conceal_seed_error()
73 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) in conceal_seed_error()
87 if (!(io_read32(rng_base + RNG_CR) & RNG_CR_RNGEN)) { in stm32_rng_read_raw()
97 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) in stm32_rng_read_raw()
101 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) { in stm32_rng_read_raw()
108 uint32_t data32 = io_read32(rng_base + RNG_DR); in stm32_rng_read_raw()
A Dcdns_uart.c71 while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_flush()
80 return !(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_have_rx_data()
90 return io_read32(base + CDNS_UART_FIFO) & 0xff; in cdns_uart_getchar()
98 while (io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_putc()
A Dmvebu_uart.c76 while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY)) in mvebu_uart_flush()
84 return (io_read32(base + UART_STATUS_REG) & UART_RX_READY); in mvebu_uart_have_rx_data()
93 return io_read32(base + UART_RX_REG) & 0xff; in mvebu_uart_getchar()
103 tmp = io_read32(base + UART_STATUS_REG); in mvebu_uart_putc()
A Dhi16xx_uart.c73 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_flush()
82 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_putc()
93 return (io_read32(base + UART_USR) & UART_USR_RFNE_BIT); in hi16xx_uart_have_rx_data()
102 return io_read32(base + UART_RBR) & 0xFF; in hi16xx_uart_getchar()
A Dstm32_i2c.c321 cfg->cr1 = io_read32(base + I2C_CR1); in save_cfg()
322 cfg->cr2 = io_read32(base + I2C_CR2); in save_cfg()
323 cfg->oar1 = io_read32(base + I2C_OAR1); in save_cfg()
324 cfg->oar2 = io_read32(base + I2C_OAR2); in save_cfg()
325 cfg->timingr = io_read32(base + I2C_TIMINGR); in save_cfg()
362 DMSG("CR1: %#"PRIx32, io_read32(base + I2C_CR1)); in dump_i2c()
363 DMSG("CR2: %#"PRIx32, io_read32(base + I2C_CR2)); in dump_i2c()
364 DMSG("OAR1: %#"PRIx32, io_read32(base + I2C_OAR1)); in dump_i2c()
850 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) in i2c_flush_txdr()
900 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) in i2c_ack_failed()
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A Dimx_lpuart.c37 while (io_read32(base + STAT) & STAT_RDRF) in imx_lpuart_getchar()
40 ch = io_read32(base + DATA) & 0x3ff; in imx_lpuart_getchar()
42 if (io_read32(base + STAT) & STAT_OR) in imx_lpuart_getchar()
52 while (!(io_read32(base + STAT) & STAT_TDRE)) in imx_lpuart_putc()
A Dbcm_sotp.c47 while (!(io_read32(addr) & bit)) in otp_status_done_wait()
106 read_data = io_read32(bcm_sotp_base + SOTP_RDDATA_1); in bcm_iproc_sotp_mem_read()
108 read_data |= io_read32(bcm_sotp_base + SOTP_RDDATA_0); in bcm_iproc_sotp_mem_read()
110 reg_val = io_read32(bcm_sotp_base + SOTP_STATUS_1); in bcm_iproc_sotp_mem_read()
A Dpl011.c96 while ((io_read32(base + UART_CR) & UART_CR_UARTEN) && in pl011_flush()
97 !(io_read32(base + UART_FR) & UART_FR_TXFE)) in pl011_flush()
105 return !(io_read32(base + UART_FR) & UART_FR_RXFE); in pl011_have_rx_data()
114 return io_read32(base + UART_DR) & 0xff; in pl011_getchar()
122 while (io_read32(base + UART_FR) & UART_FR_TXFF) in pl011_putc()
A Dstm32_gpio.c68 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
71 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; in get_gpio_cfg()
73 cfg->ospeed = (io_read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
76 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
79 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; in get_gpio_cfg()
82 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & in get_gpio_cfg()
85 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> in get_gpio_cfg()
379 uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & in valid_gpio_config()
401 if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin)) in stm32_gpio_get_input_level()
/optee_os/core/arch/arm/plat-imx/pm/
A Dgpcv2.c21 uint32_t val = io_read32(gpc_base() + offset) & (~GPC_PGC_PCG_MASK); in imx_gpcv2_set_core_pgc()
31 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ); in imx_gpcv2_set_core1_pdn_by_software()
39 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ) & in imx_gpcv2_set_core1_pdn_by_software()
48 uint32_t val = io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ); in imx_gpcv2_set_core1_pup_by_software()
56 while ((io_read32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ) & in imx_gpcv2_set_core1_pup_by_software()
A Dpsci.c78 val = io_read32(va + SRC_A7RCR1); in psci_cpu_on()
87 val = io_read32(va + SRC_SCR); in psci_cpu_on()
131 wfi = io_read32(gpr5) & ARM_WFI_STAT_MASK(cpu); in psci_affinity_info()
142 while (io_read32(va + SRC_GPR1_MX7 + cpu * 8 + 4) != UINT_MAX) in psci_affinity_info()
145 val = io_read32(va + SRC_A7RCR1); in psci_affinity_info()
149 while (io_read32(va + SRC_GPR1 + cpu * 8 + 4) != UINT32_MAX) in psci_affinity_info()
153 val = io_read32(va + SRC_SCR); in psci_affinity_info()
/optee_os/core/arch/arm/plat-rockchip/
A Dpsci_rk322x.c105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock()
111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock()
125 dram_d.cru_clksel0 = io_read32(va_base + CRU_CLKSEL_CON(0)); in plls_power_down()
126 dram_d.cru_clksel1 = io_read32(va_base + CRU_CLKSEL_CON(1)); in plls_power_down()
127 dram_d.cru_clksel10 = io_read32(va_base + CRU_CLKSEL_CON(10)); in plls_power_down()
128 dram_d.cru_clksel21 = io_read32(va_base + CRU_CLKSEL_CON(21)); in plls_power_down()
129 dram_d.cru_mode_con = io_read32(va_base + CRU_MODE_CON); in plls_power_down()
209 while (!(io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && in wait_core_wfe_i()
215 return io_read32(va_base + GRF_CPU_STATUS1) & wfei_mask; in wait_core_wfe_i()
223 val = io_read32(va_base + CRU_SOFTRST_CON(0)); in core_held_in_reset()
[all …]
/optee_os/core/drivers/clk/sam/
A Dat91_main.c39 uint32_t status = io_read32(osc->base + AT91_PMC_SR); in pmc_main_rc_osc_ready()
47 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_enable()
65 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_disable()
123 uint32_t status = io_read32(pmc->base + AT91_PMC_SR); in pmc_main_osc_ready()
131 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_enable()
152 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_disable()
198 while (!(io_read32(base + AT91_CKGR_MCFR) & AT91_PMC_MAINRDY)) in clk_main_probe_frequency()
213 mcfr = io_read32(base + AT91_CKGR_MCFR); in clk_main_get_rate()
222 uint32_t status = io_read32(base + AT91_PMC_SR); in clk_sam9x5_main_ready()
253 tmp = io_read32(pmc->base + AT91_CKGR_MOR); in clk_sam9x5_main_set_parent()
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/optee_os/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_syscfg.c57 while (!(io_read32(syscfg_base + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) in stm32mp_syscfg_enable_io_compensation()
66 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(syscfg_base + SYSCFG_CMPCR)); in stm32mp_syscfg_enable_io_compensation()
74 value = io_read32(syscfg_base + SYSCFG_CMPCR) >> in stm32mp_syscfg_disable_io_compensation()
80 value = io_read32(syscfg_base + SYSCFG_CMPCR) | in stm32mp_syscfg_disable_io_compensation()
85 DMSG("SYSCFG.cmpcr = %#"PRIx32, io_read32(syscfg_base + SYSCFG_CMPCR)); in stm32mp_syscfg_disable_io_compensation()
A Dstm32mp1_rcc.c47 while (!(io_read32(rcc_base + offset) & bitmsk)) in stm32_reset_assert()
51 if (!(io_read32(rcc_base + offset) & bitmsk)) in stm32_reset_assert()
69 while ((io_read32(rcc_base + offset) & bitmsk)) in stm32_reset_deassert()
73 if (io_read32(rcc_base + offset) & bitmsk) in stm32_reset_deassert()
/optee_os/core/arch/arm/plat-sunxi/
A Dmain.c109 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
110 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
111 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
118 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); in tzpc_init()
119 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); in tzpc_init()
120 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); in tzpc_init()
/optee_os/core/include/
A Dio.h48 static inline uint32_t io_read32(vaddr_t addr) in io_read32() function
65 io_write32(addr, (io_read32(addr) & ~mask) | (val & mask)); in io_mask32()
130 io_write32(addr, io_read32(addr) | set_mask); in io_setbits32()
135 io_write32(addr, io_read32(addr) & ~clear_mask); in io_clrbits32()
141 io_write32(addr, (io_read32(addr) & ~clear_mask) | set_mask); in io_clrsetbits32()
/optee_os/core/arch/arm/plat-hikey/
A Dmain.c71 io_read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); in spi_init()
78 read_val = io_read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); in spi_init()
90 io_read32(peri_base + PERI_SC_PERIPH_CLKEN3)); in spi_init()
93 io_read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); in spi_init()

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