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Searched refs:io_write32 (Results 1 – 25 of 81) sorted by relevance

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/optee_os/core/arch/arm/plat-zynq7k/
A Dmain.c75 io_write32(SECURITY2_SDIO0, ACCESS_BITS_ALL); in plat_primary_init_early()
77 io_write32(SECURITY4_QSPI, ACCESS_BITS_ALL); in plat_primary_init_early()
80 io_write32(SLCR_UNLOCK, SLCR_UNLOCK_MAGIC); in plat_primary_init_early()
83 io_write32(SLCR_TZ_DMA_NS, ACCESS_BITS_ALL); in plat_primary_init_early()
86 io_write32(SLCR_TZ_GEM, ACCESS_BITS_ALL); in plat_primary_init_early()
87 io_write32(SLCR_TZ_SDIO, ACCESS_BITS_ALL); in plat_primary_init_early()
88 io_write32(SLCR_TZ_USB, ACCESS_BITS_ALL); in plat_primary_init_early()
90 io_write32(SLCR_LOCK, SLCR_LOCK_MAGIC); in plat_primary_init_early()
114 io_write32(pl310_base + PL310_CTRL, 0); in arm_cl2_config()
137 io_write32(pl310_base + PL310_CTRL, 1); in arm_cl2_enable()
[all …]
/optee_os/core/arch/arm/plat-rockchip/
A Dpsci_rk322x.c70 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_disable()
81 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_restore()
137 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_power_down()
147 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_power_down()
178 io_write32(va_base + CRU_CLKSEL_CON(0), in plls_restore()
180 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_restore()
189 io_write32(va_base + CRU_CLKSEL_CON(0), in plls_restore()
191 io_write32(va_base + CRU_CLKSEL_CON(1), in plls_restore()
195 io_write32(va_base + CRU_MODE_CON, in plls_restore()
197 io_write32(va_base + CRU_MODE_CON, in plls_restore()
[all …]
A Dplatform_rk322x.c28 io_write32(ddrsgrf_base + DDR_SGRF_DDR_CON(0), DDR_RGN0_NS); in platform_secure_init()
31 io_write32(sgrf_base + SGRF_SOC_CON(7), SLAVE_ALL_NS); in platform_secure_init()
32 io_write32(sgrf_base + SGRF_SOC_CON(8), SLAVE_ALL_NS); in platform_secure_init()
33 io_write32(sgrf_base + SGRF_SOC_CON(9), SLAVE_ALL_NS); in platform_secure_init()
34 io_write32(sgrf_base + SGRF_SOC_CON(10), SLAVE_ALL_NS); in platform_secure_init()
/optee_os/core/arch/arm/plat-stm/
A Dmain.c102 io_write32(pl310 + PL310_CTRL, 0); in arm_cl2_config()
105 io_write32(pl310 + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); in arm_cl2_config()
107 io_write32(pl310 + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
109 io_write32(pl310 + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
121 io_write32(SCU_BASE + SCU_SAC, SCU_SAC_INIT); in plat_primary_init_early()
122 io_write32(SCU_BASE + SCU_NSAC, SCU_NSAC_INIT); in plat_primary_init_early()
123 io_write32(SCU_BASE + SCU_FILT_EA, CPU_PORT_FILT_END); in plat_primary_init_early()
124 io_write32(SCU_BASE + SCU_FILT_SA, CPU_PORT_FILT_START); in plat_primary_init_early()
125 io_write32(SCU_BASE + SCU_CTRL, SCU_CTRL_INIT); in plat_primary_init_early()
128 io_write32(pl310_base() + PL310_ADDR_FILT_START, in plat_primary_init_early()
[all …]
/optee_os/core/drivers/
A Ddra7_rng.c98 io_write32(rng + RNG_ALARMMASK, 0x0); in hw_get_random_byte()
99 io_write32(rng + RNG_ALARMSTOP, 0x0); in hw_get_random_byte()
101 io_write32(rng + RNG_FRODETUNE, tune ^ alarm); in hw_get_random_byte()
103 io_write32(rng + RNG_FROENABLE, RNG_FRO_MASK); in hw_get_random_byte()
105 io_write32(rng + RNG_INTACK, SHUTDOWN_OFLO); in hw_get_random_byte()
114 io_write32(rng + RNG_INTACK, RNG_READY); in hw_get_random_byte()
154 io_write32(rng + RNG_CONFIG, val); in dra7_rng_init()
157 io_write32(rng + RNG_FRODETUNE, 0x0); in dra7_rng_init()
160 io_write32(rng + RNG_FROENABLE, 0xffffff); in dra7_rng_init()
174 io_write32(rng + RNG_ALARMCNT, val); in dra7_rng_init()
[all …]
A Dhi16xx_uart.c86 io_write32(base + UART_THR, ch & 0xFF); in hi16xx_uart_putc()
122 io_write32(base + UART_FCR, UART_FCR_FIFO_EN); in hi16xx_uart_init()
125 io_write32(base + UART_LCR, UART_LCR_DLAB); in hi16xx_uart_init()
128 io_write32(base + UART_DLL, freq_div & 0xFF); in hi16xx_uart_init()
131 io_write32(base + UART_DLH, (freq_div >> 8) & 0xFF); in hi16xx_uart_init()
134 io_write32(base + UART_LCR, UART_LCR_DLS8); in hi16xx_uart_init()
137 io_write32(base + UART_IEL, 0); in hi16xx_uart_init()
A Dsp805_wdt.c52 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_config()
53 io_write32(base + WDT_LOAD_OFFSET, pd->load_val); in sp805_config()
54 io_write32(base + WDT_INTCLR_OFFSET, WDT_INT_CLR); in sp805_config()
57 io_write32(base + WDT_CONTROL_OFFSET, in sp805_config()
60 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_config()
80 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_disable()
81 io_write32(base + WDT_CONTROL_OFFSET, 0); in sp805_disable()
82 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_disable()
A Dgic.c109 io_write32(gicc_base + GICC_CTLR, 0); in probe_max_it()
119 io_write32(gicd_base + GICD_ICENABLER(i), ~old_reg); in probe_max_it()
131 io_write32(gicc_base + GICC_CTLR, old_ctlr); in probe_max_it()
158 io_write32(gd->gicc_base + GICC_PMR, 0x80); in gic_cpu_init()
161 io_write32(gd->gicc_base + GICC_CTLR, in gic_cpu_init()
202 io_write32(gd->gicc_base + GICC_PMR, 0x80); in gic_init()
262 io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask); in gic_it_add()
289 io_write32(itargetsr, target); in gic_it_set_cpu_mask()
317 io_write32(base + GICD_ISENABLER(idx), mask); in gic_it_enable()
357 io_write32(gd->gicd_base + GICD_SGIR, mask); in gic_it_raise_sgi()
[all …]
A Dzynqmp_csu_aes.c218 io_write32(csu + ZYNQMP_CSU_SSS_CFG_OFFSET, in aes_prepare_op()
222 io_write32(aes + AES_RESET_OFFSET, AES_RESET_SET); in aes_prepare_op()
223 io_write32(aes + AES_RESET_OFFSET, AES_RESET_CLR); in aes_prepare_op()
226 io_write32(aes + AES_KEY_CLR_OFFSET, 0); in aes_prepare_op()
227 io_write32(aes + AES_KEY_SRC_OFFSET, key); in aes_prepare_op()
228 io_write32(aes + AES_KEY_LOAD_OFFSET, AES_KEY_LOAD); in aes_prepare_op()
236 io_write32(aes + AES_CFG_OFFSET, in aes_prepare_op()
240 io_write32(csu + ZYNQMP_CSU_DMA_RESET_OFFSET, ZYNQMP_CSU_DMA_RESET_SET); in aes_prepare_op()
244 io_write32(aes + AES_START_MSG_OFFSET, AES_START_MSG); in aes_prepare_op()
271 io_write32(aes + AES_KEY_CLR_OFFSET, val); in aes_done_op()
[all …]
A Dpl011.c126 io_write32(base + UART_DR, ch); in pl011_putc()
148 io_write32(base + UART_RSR_ECR, 0); in pl011_init()
150 io_write32(base + UART_CR, 0); in pl011_init()
155 io_write32(base + UART_IBRD, divisor >> 6); in pl011_init()
156 io_write32(base + UART_FBRD, divisor & 0x3f); in pl011_init()
160 io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8); in pl011_init()
163 io_write32(base + UART_IMSC, UART_IMSC_RXIM | UART_IMSC_RTIM); in pl011_init()
166 io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE); in pl011_init()
A Dimx_wdog.c57 io_write32(wdog_base + WDOG_CNT, UNLOCK); in imx_wdog_restart()
59 io_write32(wdog_base + WDOG_CS, val | WDOG_CS_EN); in imx_wdog_restart()
61 io_write32(wdog_base + WDOG_CNT, UNLOCK); in imx_wdog_restart()
62 io_write32(wdog_base + WDOG_TOVAL, 1000); in imx_wdog_restart()
63 io_write32(wdog_base + WDOG_CNT, REFRESH); in imx_wdog_restart()
A Dzynqmp_csu_puf.c39 io_write32(puf + PUF_CFG0_OFFSET, PUF_CFG0_DEFAULT); in zynqmp_csu_puf_regenerate()
40 io_write32(puf + PUF_SHUT_OFFSET, PUF_SHUT_DEFAULT); in zynqmp_csu_puf_regenerate()
41 io_write32(puf + PUF_CMD_OFFSET, PUF_REGENERATION); in zynqmp_csu_puf_regenerate()
58 io_write32(puf + PUF_CMD_OFFSET, PUF_RESET); in zynqmp_csu_puf_reset()
A Dtzc380.c62 io_write32(base + ACTION_OFF, action); in tzc_write_action()
73 io_write32(base + REGION_SETUP_LOW_OFF(region), val); in tzc_write_region_base_low()
79 io_write32(base + REGION_SETUP_HIGH_OFF(region), val); in tzc_write_region_base_high()
90 io_write32(base + REGION_ATTRIBUTES_OFF(region), val); in tzc_write_region_attributes()
116 io_write32(base + SECURITY_INV_EN_OFF, 1); in tzc_security_inversion_en()
158 io_write32(base + INT_CLEAR, 0); in tzc_int_clear()
304 io_write32(tzc.base + LOCKDOWN_RANGE_OFF, val); in tzc_regions_lockdown()
310 io_write32(tzc.base + LOCKDOWN_SELECT_OFF, val); in tzc_regions_lockdown()
A Dmvebu_uart.c107 io_write32(base + UART_TX_REG, ch); in mvebu_uart_putc()
135 io_write32(base + UART_POSSR_REG, 0); in mvebu_uart_init()
138 io_write32(base + UART_CTRL_REG, in mvebu_uart_init()
142 io_write32(base + UART_CTRL_REG, 0); in mvebu_uart_init()
/optee_os/core/arch/arm/plat-imx/
A Dimx_pl310.c33 io_write32(pl310_base + PL310_CTRL, 0); in arm_cl2_config()
35 io_write32(pl310_base + PL310_TAG_RAM_CTRL, PL310_TAG_RAM_CTRL_INIT); in arm_cl2_config()
36 io_write32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); in arm_cl2_config()
37 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
58 io_write32(pl310_base + PL310_PREFETCH_CTRL, val); in arm_cl2_config()
60 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
71 io_write32(pl310_base + PL310_CTRL, 1); in arm_cl2_enable()
106 io_write32(base + PL310_DEBUG_CTRL, 0); in pl310_enable_writeback()
116 io_write32(base + PL310_DEBUG_CTRL, val); in pl310_disable_writeback()
/optee_os/core/arch/arm/plat-hikey/
A Dmain.c69 io_write32(peri_base + PERI_SC_PERIPH_RSTDIS3, shifted_val); in spi_init()
88 io_write32(peri_base + PERI_SC_PERIPH_CLKEN3, shifted_val); in spi_init()
105 io_write32(pmx0_base + PMX0_IOMG104, PINMUX_SPI); in spi_init()
106 io_write32(pmx0_base + PMX0_IOMG105, PINMUX_SPI); in spi_init()
107 io_write32(pmx0_base + PMX0_IOMG106, PINMUX_SPI); in spi_init()
108 io_write32(pmx0_base + PMX0_IOMG107, PINMUX_SPI); in spi_init()
111 io_write32(pmx1_base + PMX1_IOCG104, PINCFG_NOPULL); in spi_init()
112 io_write32(pmx1_base + PMX1_IOCG105, PINCFG_NOPULL); in spi_init()
113 io_write32(pmx1_base + PMX1_IOCG106, PINCFG_NOPULL); in spi_init()
114 io_write32(pmx1_base + PMX1_IOCG107, PINCFG_NOPULL); in spi_init()
/optee_os/core/arch/arm/plat-sam/
A Dsam_pl310.c54 io_write32(pl310_base + PL310_CTRL, 0); in arm_cl2_config()
55 io_write32(sam_sfr_base() + AT91_SFR_L2CC_HRAMC, 0x1); in arm_cl2_config()
56 io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); in arm_cl2_config()
57 io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); in arm_cl2_config()
58 io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); in arm_cl2_config()
67 io_write32(pl310_base + PL310_CTRL, 1); in arm_cl2_enable()
/optee_os/core/arch/arm/plat-ti/
A Dsm_platform_handler_a9.c60 io_write32(pl310_base() + PL310_DEBUG_CTRL, smc_args->a1); in ti_sip_handler()
69 io_write32(pl310_base() + PL310_CTRL, smc_args->a1); in ti_sip_handler()
73 io_write32(pl310_base() + PL310_AUX_CTRL, smc_args->a1); in ti_sip_handler()
77 io_write32(pl310_base() + PL310_TAG_RAM_CTRL, smc_args->a1); in ti_sip_handler()
78 io_write32(pl310_base() + PL310_DATA_RAM_CTRL, smc_args->a2); in ti_sip_handler()
82 io_write32(pl310_base() + PL310_PREFETCH_CTRL, smc_args->a1); in ti_sip_handler()
/optee_os/core/arch/arm/plat-bcm/
A Dbcm_elog.c32 io_write32(base + BCM_ELOG_OFF_OFFSET, offset); in bcm_elog_putchar()
33 io_write32(base + BCM_ELOG_LEN_OFFSET, len); in bcm_elog_putchar()
54 io_write32(base + BCM_ELOG_SIG_OFFSET, BCM_ELOG_SIG_VAL); in bcm_elog_init()
55 io_write32(base + BCM_ELOG_OFF_OFFSET, BCM_ELOG_HEADER_LEN); in bcm_elog_init()
56 io_write32(base + BCM_ELOG_LEN_OFFSET, 0); in bcm_elog_init()
/optee_os/core/arch/arm/plat-imx/drivers/
A Dimx_scu.c22 io_write32(scu_base + SCU_INV_SEC, SCU_INV_CTRL_INIT); in scu_init()
23 io_write32(scu_base + SCU_SAC, SCU_SAC_CTRL_INIT); in scu_init()
24 io_write32(scu_base + SCU_NSAC, SCU_NSAC_CTRL_INIT); in scu_init()
27 io_write32(scu_base + SCU_CTRL, io_read32(scu_base + SCU_CTRL) | 0x1); in scu_init()
/optee_os/core/arch/arm/plat-imx/pm/
A Dpsci.c73 io_write32(va + SRC_GPR1_MX7 + core_idx * 8, val); in psci_cpu_on()
81 io_write32(va + SRC_A7RCR1, val); in psci_cpu_on()
84 io_write32(va + SRC_GPR1 + core_idx * 8, val); in psci_cpu_on()
90 io_write32(va + SRC_SCR, val); in psci_cpu_on()
147 io_write32(va + SRC_A7RCR1, val); in psci_affinity_info()
156 io_write32(va + SRC_SCR, val); in psci_affinity_info()
171 io_write32(snvs_base + SNVS_LPCR_OFF, in psci_system_off()
A Dgpcv2.c26 io_write32(gpc_base() + offset, val); in imx_gpcv2_set_core_pgc()
37 io_write32(gpc_base() + GPC_CPU_PGC_SW_PDN_REQ, val); in imx_gpcv2_set_core1_pdn_by_software()
54 io_write32(gpc_base() + GPC_CPU_PGC_SW_PUP_REQ, val); in imx_gpcv2_set_core1_pup_by_software()
/optee_os/core/arch/arm/plat-sunxi/
A Dpsci.c93 io_write32(cpucfg + REG_CPUCFG_PRIV0, val); in psci_cpu_on()
97 io_write32(cpucfg + REG_CPUCFG_CPU_RST(core_idx), 0); in psci_cpu_on()
112 io_write32(base + REG_PRCM_CPU_PWR_CLAMP(core_idx), tmpff); in psci_cpu_on()
123 io_write32(cpucfg + REG_CPUCFG_CPU_RST(core_idx), 0x03); in psci_cpu_on()
158 io_write32(base + REG_PRCM_CPU_PWR_CLAMP(core_id), 0xff); in psci_cpu_off()
/optee_os/core/arch/arm/plat-ls/
A Dmain.c80 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, in plat_primary_init_early()
84 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, in plat_primary_init_early()
96 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); in plat_primary_init_early()
99 io_write32(CSU_BASE + CSU_CSL30, in plat_primary_init_early()
101 io_write32(CSU_BASE + CSU_CSL37, in plat_primary_init_early()
/optee_os/core/arch/arm/plat-aspeed/
A Dplatform_ast2600.c114 io_write32(ahbc_virt + AHBC_TZM_PERM(0), in plat_primary_init_early()
116 io_write32(ahbc_virt + AHBC_TZM_ED(0), in plat_primary_init_early()
118 io_write32(ahbc_virt + AHBC_TZM_ST(0), in plat_primary_init_early()
120 io_write32(ahbc_virt + AHBC_REG_WR_PROT, BIT(16)); in plat_primary_init_early()

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