Searched refs:PLAT_CSS_MHU_BASE (Results 1 – 18 of 18) sorted by relevance
47 while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_start()55 assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_send()59 mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); in mhu_secure_message_send()66 while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) in mhu_secure_message_wait()80 mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); in mhu_secure_message_end()94 assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); in mhu_secure_init()
25 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,34 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),43 .db_reg_addr = PLAT_CSS_MHU_BASE54 .db_reg_addr = PLAT_CSS_MHU_BASE +65 .db_reg_addr = PLAT_CSS_MHU_BASE +
18 #define PLAT_CSS_MHU_BASE UL(0x45400000) macro19 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
17 #define PLAT_CSS_MHU_BASE UL(0x45400000) macro18 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
23 #define PLAT_CSS_MHU_BASE UL(0x2A920000) macro24 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
71 #define PLAT_CSS_MHU_BASE UL(0x45000000) macro72 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
19 #define PLAT_CSS_MHU_BASE UL(0x45000000) macro
19 #define PLAT_CSS_MHU_BASE UL(0x45400000) macro
17 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
22 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
208 #define PLAT_CSS_MHU_BASE UL(0x45400000) macro209 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
92 #define PLAT_CSS_MHU_BASE 0x45000000 macro
49 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
88 #define PLAT_CSS_MHU_BASE 0x2b1f0000 macro
240 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) macro
51 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
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