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Searched refs:enable (Results 1 – 25 of 82) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/arm/common/
A Darm_nor_psci_mem_protect.c53 unsigned long enable = (val != 0) ? 1UL : 0UL; in arm_nor_psci_write_mem_protect() local
60 if (enable == 1UL) { in arm_nor_psci_write_mem_protect()
74 if (nor_word_program(PLAT_ARM_MEM_PROT_ADDR, enable) != 0) { in arm_nor_psci_write_mem_protect()
97 int enable; in arm_nor_psci_do_dyn_mem_protect() local
99 arm_psci_read_mem_protect(&enable); in arm_nor_psci_do_dyn_mem_protect()
100 if (enable == 0) in arm_nor_psci_do_dyn_mem_protect()
117 int enable; in arm_nor_psci_do_static_mem_protect() local
119 (void) arm_psci_read_mem_protect(&enable); in arm_nor_psci_do_static_mem_protect()
120 if (enable == 0) in arm_nor_psci_do_static_mem_protect()
/tf-a-ffa_el3_spmc/plat/socionext/uniphier/
A Duniphier_cci.c37 void (*enable)(void); member
44 .enable = NULL,
49 .enable = __uniphier_cci_enable,
54 .enable = NULL,
73 if (uniphier_cci_ops.enable) in uniphier_cci_enable()
74 uniphier_cci_ops.enable(); in uniphier_cci_enable()
/tf-a-ffa_el3_spmc/plat/arm/board/tc/fdts/
A Dtc_spmc_manifest.dts56 enable-method = "psci";
67 enable-method = "psci";
74 enable-method = "psci";
81 enable-method = "psci";
88 enable-method = "psci";
95 enable-method = "psci";
102 enable-method = "psci";
109 enable-method = "psci";
A Dtc_spmc_optee_sp_manifest.dts62 enable-method = "psci";
73 enable-method = "psci";
80 enable-method = "psci";
87 enable-method = "psci";
94 enable-method = "psci";
101 enable-method = "psci";
108 enable-method = "psci";
115 enable-method = "psci";
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhisi_pwrc.c57 unsigned int val, enable; in hisi_pwrc_enable_debug() local
59 enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); in hisi_pwrc_enable_debug()
63 mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable); in hisi_pwrc_enable_debug()
67 } while (!(val & enable)); in hisi_pwrc_enable_debug()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/wdt/
A Dwdt.c71 void wdt_set_enable(int enable) in wdt_set_enable() argument
73 if (enable) in wdt_set_enable()
76 WDT_MODE_KEY | (enable ? WDT_MODE_EN : 0)); in wdt_set_enable()
A Dwdt.h14 void wdt_set_enable(int enable);
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_mem_protect.c14 u_register_t psci_mem_protect(unsigned int enable) in psci_mem_protect() argument
23 if (psci_plat_pm_ops->write_mem_protect(enable) < 0) in psci_mem_protect()
/tf-a-ffa_el3_spmc/plat/mediatek/common/drivers/gpio/
A Dmtgpio_common.c90 static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable, in mt_gpio_set_spec_pull_pupd() argument
102 if (enable == MT_GPIO_PULL_ENABLE) { in mt_gpio_set_spec_pull_pupd()
115 static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable, in mt_gpio_set_pull_pu_pd() argument
128 if (enable == MT_GPIO_PULL_ENABLE) { in mt_gpio_set_pull_pu_pd()
142 static void mt_gpio_set_pull_chip(uint32_t pin, int enable, in mt_gpio_set_pull_chip() argument
149 mt_gpio_set_spec_pull_pupd(pin, enable, select); in mt_gpio_set_pull_chip()
151 mt_gpio_set_pull_pu_pd(pin, enable, select); in mt_gpio_set_pull_chip()
/tf-a-ffa_el3_spmc/fdts/
A Dn1sdp-multi-chip.dts14 enable-method = "psci";
21 enable-method = "psci";
28 enable-method = "psci";
35 enable-method = "psci";
A Dmorello-fvp.dts53 enable-method = "psci";
60 enable-method = "psci";
67 enable-method = "psci";
74 enable-method = "psci";
A Dtc.dts86 enable-method = "psci";
96 enable-method = "psci";
106 enable-method = "psci";
116 enable-method = "psci";
126 enable-method = "psci";
136 enable-method = "psci";
146 enable-method = "psci";
156 enable-method = "psci";
A Dn1sdp.dtsi21 enable-method = "psci";
28 enable-method = "psci";
35 enable-method = "psci";
42 enable-method = "psci";
/tf-a-ffa_el3_spmc/drivers/mtd/nand/
A Dspi_nand.c84 static int spi_nand_ecc_enable(bool enable) in spi_nand_ecc_enable() argument
87 enable ? SPI_NAND_CFG_ECC_EN : 0U); in spi_nand_ecc_enable()
92 bool enable = false; in spi_nand_quad_enable() local
100 enable = true; in spi_nand_quad_enable()
104 enable ? SPI_NAND_CFG_QE : 0U); in spi_nand_quad_enable()
/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx_clock.c40 void imx_clock_gate_enable(unsigned int id, bool enable) in imx_clock_gate_enable() argument
49 if (enable) in imx_clock_gate_enable()
/tf-a-ffa_el3_spmc/plat/imx/common/include/sci/svc/misc/
A Dsci_misc_api.h367 sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable);
416 sc_bool_t enable);
/tf-a-ffa_el3_spmc/drivers/marvell/mochi/
A Dapn806_setup.c93 static void apn_sec_masters_access_en(uint32_t enable) in apn_sec_masters_access_en() argument
99 if (enable != 0) { in apn_sec_masters_access_en()
A Dap807_setup.c98 static void ap_sec_masters_access_en(uint32_t enable) in ap_sec_masters_access_en() argument
104 if (enable != 0) { in ap_sec_masters_access_en()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/include/
A Dmce_private.h161 uint8_t enable);
233 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
255 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
/tf-a-ffa_el3_spmc/drivers/brcm/
A Docotp.c119 static int bcm_otpc_ecc(uint32_t enable) in bcm_otpc_ecc() argument
127 if (!enable) in bcm_otpc_ecc()
/tf-a-ffa_el3_spmc/plat/imx/common/include/sci/svc/pm/
A Dsci_pm_api.h503 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
677 sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
/tf-a-ffa_el3_spmc/docs/security_advisories/
A Dsecurity-advisory-tfv-6.rst54 significantly more complex than the "MMU disable/enable" workaround. The latter
62 locally (for example by implementing "MMU disable/enable" itself), there is no
70 mitigation specification`_. The specification and implementation also enable
75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
93 | ``PSCI_VERSION`` with "MMU disable/enable" | 930 |
95 | ``SMCCC_ARCH_WORKAROUND_1`` with "MMU disable/enable" | 386 |
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c233 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) in nvg_cc3_ctrl() argument
251 ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); in nvg_cc3_ctrl()
/tf-a-ffa_el3_spmc/tools/marvell/doimage/secure/
A Dsec_img_7K.cfg21 jtag = { enable = true; delay = 20; };
A Dsec_img_8K.cfg21 jtag = { enable = true; delay = 20; };

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