| /tf-a-ffa_el3_spmc/plat/imx/common/ |
| A D | imx8_psci.c | 33 psci_power_state_t *req_state) in imx_validate_power_state() argument
43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
53 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) in imx_get_sys_suspend_power_state() argument
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/ |
| A D | imx8mq_psci.c | 20 psci_power_state_t *req_state) in imx_validate_power_state() argument
30 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
31 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
35 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
36 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
98 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) in imx_get_sys_suspend_power_state() argument
103 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; in imx_get_sys_suspend_power_state()
105 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/arm/common/ |
| A D | arm_pm.c | 25 psci_power_state_t *req_state) in arm_validate_power_state() argument
31 assert(req_state != NULL); in arm_validate_power_state()
45 req_state->pwr_domain_state[ARM_PWR_LVL0] = in arm_validate_power_state()
49 req_state->pwr_domain_state[i] = in arm_validate_power_state()
69 psci_power_state_t *req_state) in arm_validate_power_state() argument
74 assert(req_state != NULL); in arm_validate_power_state()
95 req_state->pwr_domain_state[i++] = state_id & in arm_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/allwinner/common/ |
| A D | sunxi_scpi_pm.c | 137 psci_power_state_t *req_state) in sunxi_validate_power_state() argument
142 assert(req_state != NULL); in sunxi_validate_power_state()
158 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in sunxi_validate_power_state()
166 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_validate_power_state()
171 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; in sunxi_validate_power_state()
177 static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state) in sunxi_get_sys_suspend_power_state() argument
179 assert(req_state != NULL); in sunxi_get_sys_suspend_power_state()
182 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/xilinx/versal/ |
| A D | plat_psci.c | 186 psci_power_state_t *req_state) in versal_validate_power_state() argument
192 assert(req_state); in versal_validate_power_state()
196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
198 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
212 static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state) in versal_get_sys_suspend_power_state() argument
214 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
215 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/ |
| A D | plat_psci.c | 161 psci_power_state_t *req_state) in zynqmp_validate_power_state() argument
167 assert(req_state); in zynqmp_validate_power_state()
171 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
182 void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) in zynqmp_get_sys_suspend_power_state() argument
184 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
185 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/hisilicon/poplar/ |
| A D | plat_pm.c | 110 psci_power_state_t *req_state) in poplar_validate_power_state() argument
116 assert(req_state); in poplar_validate_power_state()
120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
143 static void poplar_get_sys_suspend_power_state(psci_power_state_t *req_state) in poplar_get_sys_suspend_power_state() argument
148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/imx/imx8m/ |
| A D | imx8m_psci_common.c | 68 psci_power_state_t *req_state) in imx_validate_power_state() argument
78 CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
79 CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; in imx_validate_power_state()
83 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
84 CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE; in imx_validate_power_state()
147 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) in imx_get_sys_suspend_power_state() argument
152 req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; in imx_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_pm.c | 37 static void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) in tegra_get_sys_suspend_power_state() argument
41 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; in tegra_get_sys_suspend_power_state()
240 psci_power_state_t *req_state) in tegra_validate_power_state() argument
242 assert(req_state != NULL); in tegra_validate_power_state()
244 return tegra_soc_validate_power_state(power_state, req_state); in tegra_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/imx/common/include/ |
| A D | plat_imx8.h | 29 psci_power_state_t *req_state);
30 void imx_get_sys_suspend_power_state(psci_power_state_t *req_state);
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| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey/ |
| A D | hikey_pm.c | 163 static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state) in hikey_get_sys_suspend_power_state() argument
168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey_get_sys_suspend_power_state()
215 psci_power_state_t *req_state) in hikey_validate_power_state() argument
221 assert(req_state); in hikey_validate_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
239 req_state->pwr_domain_state[i] = in hikey_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/renesas/common/ |
| A D | plat_pm.c | 242 psci_power_state_t *req_state) in rcar_validate_power_state() argument
252 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
255 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
265 static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state) in rcar_get_sys_suspend_power_state() argument
274 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
279 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
281 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/arm/css/common/ |
| A D | css_pm.c | 267 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) in css_get_sys_suspend_power_state() argument
278 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; in css_get_sys_suspend_power_state()
295 psci_power_state_t *req_state) in css_validate_power_state() argument
298 rc = arm_validate_power_state(power_state, req_state); in css_validate_power_state()
314 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = in css_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/rockchip/common/ |
| A D | plat_pm.c | 133 psci_power_state_t *req_state) in rockchip_validate_power_state() argument
139 assert(req_state); in rockchip_validate_power_state()
153 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
157 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
161 req_state->pwr_domain_state[i] = in rockchip_validate_power_state()
172 void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state) in rockchip_get_sys_suspend_power_state() argument
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/ |
| A D | plat_pm.c | 434 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) in plat_get_sys_suspend_power_state() argument
439 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_get_sys_suspend_power_state()
470 psci_power_state_t *req_state) in plat_validate_power_state() argument
476 assert(req_state); in plat_validate_power_state()
490 req_state->pwr_domain_state[MTK_PWR_LVL0] = in plat_validate_power_state()
494 req_state->pwr_domain_state[i] = in plat_validate_power_state()
508 psci_power_state_t *req_state) in plat_validate_power_state() argument
513 assert(req_state); in plat_validate_power_state()
534 req_state->pwr_domain_state[i++] = state_id & in plat_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/qti/common/src/ |
| A D | qti_pm.c | 79 psci_power_state_t *req_state) in qti_validate_power_state() argument
84 assert(req_state); in qti_validate_power_state()
105 req_state->pwr_domain_state[i++] = state_id & in qti_validate_power_state()
230 void qti_get_sys_suspend_power_state(psci_power_state_t *req_state) in qti_get_sys_suspend_power_state() argument
246 req_state->pwr_domain_state[i++] = in qti_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/intel/soc/common/ |
| A D | socfpga_psci.c | 177 psci_power_state_t *req_state) in socfpga_validate_power_state() argument
190 void socfpga_get_sys_suspend_power_state(psci_power_state_t *req_state) in socfpga_get_sys_suspend_power_state() argument
192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/ |
| A D | hikey960_pm.c | 139 psci_power_state_t *req_state) in hikey960_validate_power_state() argument
145 assert(req_state); in hikey960_validate_power_state()
159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()
163 req_state->pwr_domain_state[i] = in hikey960_validate_power_state()
289 static void hikey960_get_sys_suspend_power_state(psci_power_state_t *req_state) in hikey960_get_sys_suspend_power_state() argument
294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/ |
| A D | fvp_pm.c | 371 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) in fvp_get_sys_suspend_power_state() argument
376 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; in fvp_get_sys_suspend_power_state()
389 psci_power_state_t *req_state) in fvp_validate_power_state() argument
392 rc = arm_validate_power_state(power_state, req_state); in fvp_validate_power_state()
399 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; in fvp_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/st/stm32mp1/ |
| A D | stm32mp1_pm.c | 162 psci_power_state_t *req_state) in stm32_validate_power_state() argument
178 req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET; in stm32_validate_power_state()
179 req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN; in stm32_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8183/ |
| A D | plat_pm.c | 442 psci_power_state_t *req_state) in plat_mtk_validate_power_state() argument
447 assert(req_state); in plat_mtk_validate_power_state()
471 req_state->pwr_domain_state[i++] = state_id & in plat_mtk_validate_power_state()
482 psci_power_state_t *req_state) in plat_mtk_validate_power_state() argument
488 assert(req_state); in plat_mtk_validate_power_state()
502 req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET; in plat_mtk_validate_power_state()
507 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_mtk_validate_power_state()
544 static void plat_mtk_get_sys_suspend_power_state(psci_power_state_t *req_state) in plat_mtk_get_sys_suspend_power_state() argument
549 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_mtk_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/qemu/qemu_sbsa/ |
| A D | sbsa_pm.c | 77 psci_power_state_t *req_state) in qemu_validate_power_state() argument
82 assert(req_state != NULL); in qemu_validate_power_state()
105 req_state->pwr_domain_state[i++] = state_id & in qemu_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/qemu/common/ |
| A D | qemu_pm.c | 70 psci_power_state_t *req_state) in qemu_validate_power_state() argument
75 assert(req_state); in qemu_validate_power_state()
96 req_state->pwr_domain_state[i++] = state_id & in qemu_validate_power_state()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8192/ |
| A D | plat_pm.c | 296 psci_power_state_t *req_state) in plat_validate_power_state() argument
303 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; in plat_validate_power_state()
315 req_state->pwr_domain_state[i] = s; in plat_validate_power_state()
323 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) in plat_get_sys_suspend_power_state() argument
329 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; in plat_get_sys_suspend_power_state()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8195/ |
| A D | plat_pm.c | 291 psci_power_state_t *req_state) in plat_validate_power_state() argument
302 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; in plat_validate_power_state()
314 req_state->pwr_domain_state[i] = s; in plat_validate_power_state()
322 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) in plat_get_sys_suspend_power_state() argument
328 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; in plat_get_sys_suspend_power_state()
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