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/tf-a-ffa_el3_spmc/bl2/aarch64/
A Dbl2_el3_entrypoint.S26 mov x20, x0
44 mov x0, x20
77 mov x20,x0
98 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
102 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
103 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
104 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
105 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
A Dbl2_entrypoint.S22 mov x20, x0
114 mov x0, x20
/tf-a-ffa_el3_spmc/bl31/aarch64/
A Dbl31_entrypoint.S30 mov x20, x0
76 mov x20, 0
86 mov x0, x20
219 mov x20, x30
221 mov x30, x20
A Druntime_exceptions.S227 mov x20, sp
272 mov x2, x20
/tf-a-ffa_el3_spmc/bl1/aarch64/
A Dbl1_exceptions.S176 mov x20, x1
178 mov x0, x20
181 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
198 mov x0, x20
201 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
202 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
203 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
204 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
/tf-a-ffa_el3_spmc/services/spd/tspd/
A Dtspd_helpers.S28 stp x19, x20, [sp, #TSPD_C_RT_CTX_X19]
62 ldp x19, x20, [x0, #(TSPD_C_RT_CTX_X19 - TSPD_C_RT_CTX_SIZE)]
/tf-a-ffa_el3_spmc/bl2u/aarch64/
A Dbl2u_entrypoint.S21 mov x20, x1
103 mov x0, x20
/tf-a-ffa_el3_spmc/services/spd/opteed/
A Dopteed_helpers.S28 stp x19, x20, [sp, #OPTEED_C_RT_CTX_X19]
62 ldp x19, x20, [x0, #(OPTEED_C_RT_CTX_X19 - OPTEED_C_RT_CTX_SIZE)]
/tf-a-ffa_el3_spmc/services/spd/tlkd/
A Dtlkd_helpers.S30 stp x19, x20, [sp, #TLKD_C_RT_CTX_X19]
63 ldp x19, x20, [x0, #(TLKD_C_RT_CTX_X19 - TLKD_C_RT_CTX_SIZE)]
/tf-a-ffa_el3_spmc/services/std_svc/spm/common/aarch64/
A Dspm_helpers.S28 stp x19, x20, [sp, #SP_C_RT_CTX_X19]
58 ldp x19, x20, [x0, #(SP_C_RT_CTX_X19 - SP_C_RT_CTX_SIZE)]
/tf-a-ffa_el3_spmc/services/std_svc/spmd/aarch64/
A Dspmd_helpers.S28 stp x19, x20, [sp, #SPMD_C_RT_CTX_X19]
57 ldp x19, x20, [x0, #(SPMD_C_RT_CTX_X19 - SPMD_C_RT_CTX_SIZE)]
/tf-a-ffa_el3_spmc/plat/rockchip/common/aarch64/
A Dplat_helpers.S106 and x20, x0, #MPIDR_CLUSTER_MASK
107 mov x0, x20
114 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT
/tf-a-ffa_el3_spmc/lib/libc/aarch64/
A Dsetjmp.S20 stp x19, x20, [x0, #JMP_CTX_X19]
49 ldp x19, x20, [x0, #JMP_CTX_X19]
/tf-a-ffa_el3_spmc/lib/psci/aarch64/
A Dpsci_helpers.S32 stp x19, x20, [sp,#-16]!
70 ldp x19, x20, [sp], #16
/tf-a-ffa_el3_spmc/services/spd/trusty/
A Dtrusty_helpers.S20 push x19, x20
37 pop x19, x20
/tf-a-ffa_el3_spmc/plat/qti/qtiseclib/inc/
A Dqtiseclib_defs.h63 uint64_t x20; member
/tf-a-ffa_el3_spmc/plat/renesas/common/aarch64/
A Dplat_helpers.S168 mov x20, x0
189 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
/tf-a-ffa_el3_spmc/fdts/
A Dn1sdp.dtsi166 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x20 0x00000000>;
189 <0x42000000 0x29 0x00000000 0x29 0x00000000 0x20 0x00000000>;
A Dn1sdp-multi-chip.dts80 <0x42000000 0x09 0x00000000 0x409 0x00000000 0x20 0x00000000>;
A Dfvp-ve-Cortex-A5x1.dts48 reg = <0x2c000620 0x20>;
/tf-a-ffa_el3_spmc/lib/cpus/aarch64/
A Dwa_cve_2017_5715_bpiall.S36 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
300 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
/tf-a-ffa_el3_spmc/lib/el3_runtime/aarch64/
A Dcontext.S691 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
734 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */
745 stp x20, x21, [x19, #CTX_PACIAKEY_LO]
818 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
911 ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3]
918 msr S3_6_C1_C2_0, x20 /* zcr_el3 */
/tf-a-ffa_el3_spmc/plat/qti/qtiseclib/src/
A Dqtiseclib_cb_interface.c166 qti_ns_ctx->x20 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X20); in qtiseclib_cb_get_ns_ctx()
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/aarch64/
A Dlx2160a.S984 mov x20, #PMU_IPSTPCR5_OFFSET
985 ldr w14, [x1, x20]
1061 str w12, [x1, x20]
1260 mov x20, #PMU_IPSTPCR0_OFFSET
1261 str w9, [x1, x20]
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/aarch64/
A Dtegra_helpers.S239 _end: mov x0, x20

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