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/trusted-firmware-a/plat/brcm/board/stingray/driver/ext_sram_init/
A Dext_sram_init.c21 INFO(" - pnor pinmux init start.\n"); in brcm_stingray_pnor_pinmux_init()
160 INFO(" - pnor pinmux init done.\n"); in brcm_stingray_pnor_pinmux_init()
185 INFO(" - pnor sram init start.\n"); in brcm_stingray_pnor_sram_init()
188 INFO(" -- enable pnor clock\n"); in brcm_stingray_pnor_sram_init()
193 INFO(" -- reset pnor\n"); in brcm_stingray_pnor_sram_init()
233 INFO(" -- pnor set_cycles = 0x%x\n", val); in brcm_stingray_pnor_sram_init()
257 INFO(" -- pnor refresh_0 = 0x%x\n", val); in brcm_stingray_pnor_sram_init()
284 INFO(" - pnor sram init failed.\n"); in brcm_stingray_pnor_sram_init()
288 INFO(" - pnor sram init done.\n"); in brcm_stingray_pnor_sram_init()
295 INFO("%s start.\n", __func__); in ext_sram_init()
[all …]
/trusted-firmware-a/docs/plat/
A Dintel-stratix10.rst71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
73 INFO: Init HPS NOC's DDR Scheduler.
76 INFO: BL2: Doing platform setup
77 INFO: BL2: Loading image id 3
80 INFO: BL2: Loading image id 5
84 INFO: Entry point address = 0xffe1c000
85 INFO: SPSR = 0x3cd
88 INFO: ARM GICv2 driver initialized
92 INFO: Entry point address = 0x50000
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A Dpoplar.rst122 INFO: BL1: RAM 0xe1000 - 0xe7000
123 INFO: BL1: Loading BL2
127 INFO: Entry point address = 0xe9000
128 INFO: SPSR = 0x3c5
131 INFO: BL2: Loading BL31
134 INFO: BL2: Loading BL33
138 INFO: Entry point address = 0x129000
139 INFO: SPSR = 0x3cd
143 INFO: BL31: Initializing runtime services
145 INFO: Entry point address = 0x37000000
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A Dintel-agilex.rst71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
75 INFO: BL2: Doing platform setup
77 INFO: Entry point address = 0xffe1c000
78 INFO: SPSR = 0x3cd
81 INFO: ARM GICv2 driver initialized
82 INFO: BL31: Initializing runtime services
84 INFO: BL31: Preparing for EL3 exit to normal world
85 INFO: Entry point address = 0x50000
86 INFO: SPSR = 0x3c9
/trusted-firmware-a/docs/build/TF-A_2.5/_sources/plat/
A Dintel-stratix10.rst.txt71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
73 INFO: Init HPS NOC's DDR Scheduler.
76 INFO: BL2: Doing platform setup
77 INFO: BL2: Loading image id 3
80 INFO: BL2: Loading image id 5
84 INFO: Entry point address = 0xffe1c000
85 INFO: SPSR = 0x3cd
88 INFO: ARM GICv2 driver initialized
92 INFO: Entry point address = 0x50000
[all …]
A Dpoplar.rst.txt122 INFO: BL1: RAM 0xe1000 - 0xe7000
123 INFO: BL1: Loading BL2
127 INFO: Entry point address = 0xe9000
128 INFO: SPSR = 0x3c5
131 INFO: BL2: Loading BL31
134 INFO: BL2: Loading BL33
138 INFO: Entry point address = 0x129000
139 INFO: SPSR = 0x3cd
143 INFO: BL31: Initializing runtime services
145 INFO: Entry point address = 0x37000000
[all …]
A Dintel-agilex.rst.txt71 INFO: DDR: DRAM calibration success.
72 INFO: ECC is disabled.
75 INFO: BL2: Doing platform setup
77 INFO: Entry point address = 0xffe1c000
78 INFO: SPSR = 0x3cd
81 INFO: ARM GICv2 driver initialized
82 INFO: BL31: Initializing runtime services
84 INFO: BL31: Preparing for EL3 exit to normal world
85 INFO: Entry point address = 0x50000
86 INFO: SPSR = 0x3c9
/trusted-firmware-a/plat/brcm/board/stingray/src/
A Dscp_utils.c91 INFO("SCP Patch is already active.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
104 INFO("AP booted by Nitro\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
120 INFO("MCU Patch Point: 0x%x\n", in plat_bcm_bl2_plat_handle_scp_bl2()
139 INFO("SCP Patch successfully initialized.\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
144 INFO("SCP Patch version :0x%x\n", scp_patch_version); in plat_bcm_bl2_plat_handle_scp_bl2()
158 INFO("AVS voltages from cfg (including margin)\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
160 INFO("%s\tVCORE: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
164 INFO("%s\tIHOST03: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
168 INFO("%s\tIHOST12: %dmv\n", in plat_bcm_bl2_plat_handle_scp_bl2()
172 INFO("AVS settings not applicable\n"); in plat_bcm_bl2_plat_handle_scp_bl2()
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A Dpm.c40 INFO("mpidr :%lu, cpuid:%d\n", mpidr, cpuid); in brcm_pwr_domain_on()
68 INFO("Cluster #%lu entering to snoop/dvm domain\n", cluster_id); in brcm_pwr_domain_on_finish()
78 INFO("Gic Initialization done for this affinity instance\n"); in brcm_pwr_domain_on_finish()
89 INFO("System rebooting - L%d...\n", reset_type); in brcm_system_reset()
101 INFO("System rebooting - L%d...\n", reset_type); in brcm_system_reset2()
A Dbl2_setup.c168 INFO("PCIE SATA Rescal Init done\n"); in brcm_stingray_pcie_reset()
345 INFO("Regulator supply got stable\n"); in set_swreg_based_on_otp()
432 INFO("DDR ref ID by SW (Not MCB Ref ID) 0x%x\n", in board_detect_fru()
438 INFO("**** FRU board information ****\n"); in board_detect_fru()
439 INFO("Language 0x%x\n", board_info.lang); in board_detect_fru()
440 INFO("Manufacturing Date %u.%02u.%02u, %02u:%02u\n", in board_detect_fru()
444 INFO("Manufacturer %s\n", board_info.manufacturer); in board_detect_fru()
445 INFO("Product Name %s\n", board_info.product_name); in board_detect_fru()
446 INFO("Serial number %s\n", board_info.serial_number); in board_detect_fru()
447 INFO("Part number %s\n", board_info.part_number); in board_detect_fru()
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/trusted-firmware-a/plat/intel/soc/common/drivers/wdt/
A Dwatchdog.c22 INFO("Component Type : %x\r\n", mmio_read_32(WDT_COMP_VERSION)); in watchdog_info()
23 INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE)); in watchdog_info()
30 INFO("Watchdog Timer is currently enabled\n"); in watchdog_status()
31 INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR)); in watchdog_status()
33 INFO("Watchdog Timer is currently disabled\n"); in watchdog_status()
/trusted-firmware-a/plat/st/stm32mp1/
A Dbl2_plat_setup.c52 INFO("Reset reason (0x%x):\n", rstsr); in print_reset_reason()
56 INFO("System exits from STANDBY\n"); in print_reset_reason()
61 INFO("MPU exits from CSTANDBY\n"); in print_reset_reason()
67 INFO(" Power-on Reset (rst_por)\n"); in print_reset_reason()
96 INFO(" IWDG1 Reset (rst_iwdg1)\n"); in print_reset_reason()
101 INFO(" IWDG2 Reset (rst_iwdg2)\n"); in print_reset_reason()
106 INFO(" MPU Processor 0 Reset\n"); in print_reset_reason()
111 INFO(" MPU Processor 1 Reset\n"); in print_reset_reason()
116 INFO(" Pad Reset from NRST\n"); in print_reset_reason()
160 INFO("BL2 runs OP-TEE setup\n"); in bl2_platform_setup()
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/trusted-firmware-a/bl32/tsp/
A Dtsp_main.c107 INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE); in tsp_main()
108 INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE); in tsp_main()
125 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", in tsp_main()
154 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); in tsp_cpu_on_main()
155 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", in tsp_cpu_on_main()
195 INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); in tsp_cpu_off_main()
196 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", in tsp_cpu_off_main()
278 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n", in tsp_cpu_resume_main()
310 INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); in tsp_system_off_main()
342 INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); in tsp_system_reset_main()
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/trusted-firmware-a/plat/mediatek/mt6795/
A Dbl31_plat_setup.c263 INFO("mmap atf buffer : 0x%x, 0x%x\n\r", in bl31_plat_arch_setup()
275 INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n", in bl31_plat_arch_setup()
308 INFO("BL3-1: %s\n", version_string); in bl31_plat_arch_setup()
309 INFO("BL3-1: %s\n", build_message); in bl31_plat_arch_setup()
346 INFO("Kernel_EL2\n"); in bl31_plat_get_next_kernel64_ep_info()
349 INFO("Kernel_EL1\n"); in bl31_plat_get_next_kernel64_ep_info()
353 INFO("Kernel is 64Bit\n"); in bl31_plat_get_next_kernel64_ep_info()
360 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx\n", in bl31_plat_get_next_kernel64_ep_info()
396 INFO("Kernel is 32Bit\n"); in bl31_plat_get_next_kernel32_ep_info()
405 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx, r2=0x%lx\n", in bl31_plat_get_next_kernel32_ep_info()
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/trusted-firmware-a/lib/optee/
A Doptee_utils.c152 INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc); in parse_optee_header()
153 INFO("OPTEE header info:\n"); in parse_optee_header()
154 INFO(" magic=0x%x\n", header->magic); in parse_optee_header()
155 INFO(" version=0x%x\n", header->version); in parse_optee_header()
156 INFO(" arch=0x%x\n", header->arch); in parse_optee_header()
157 INFO(" flags=0x%x\n", header->flags); in parse_optee_header()
158 INFO(" nb_images=0x%x\n", header->nb_images); in parse_optee_header()
178 INFO("Invalid OPTEE header, set legacy mode.\n"); in parse_optee_header()
/trusted-firmware-a/plat/brcm/board/common/
A Dboard_arm_trusted_boot.c73 INFO("NOT AB\n"); in plat_is_trusted_boot()
77 INFO("AB\n"); in plat_is_trusted_boot()
207 INFO("NON-AB: Do not read DAUTH!\n"); in plat_get_rotpk_info()
215 INFO("readKeys (DAUTH) from BL11\n"); in plat_get_rotpk_info()
239 INFO("AB DEV: FAST AUTH!\n"); in plat_get_rotpk_info()
251 INFO("sotp_read_key (DAUTH): %i\n", ret); in plat_get_rotpk_info()
273 INFO("Use internal key hash.\n"); in plat_get_rotpk_info()
280 INFO("No hash found in SOTP\n"); in plat_get_rotpk_info()
397 INFO("CTR %i\n", nvctr); in sotp_get_trusted_nvctr()
447 INFO("NCTR %i\n", nvctr); in sotp_get_nontrusted_nvctr()
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/trusted-firmware-a/plat/nxp/common/soc_errata/
A Derrata.c15 INFO("SoC workaround for Errata A050426 was applied\n"); in soc_errata()
23 INFO("SoC workaround for DDR Errata A011396 was applied\n"); in soc_errata()
26 INFO("SoC workaround for DDR Errata A050450 was applied\n"); in soc_errata()
/trusted-firmware-a/drivers/brcm/i2c/
A Di2c.c141 INFO("SMB_CFG_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
144 INFO("SMB_TIMGCFG_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
147 INFO("SMB_ADDR_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
153 INFO("SMB_SLVFIFOCTL_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
159 INFO("SMB_MSTRCMD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
162 INFO("SMB_SLVCMD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
165 INFO("SMB_EVTEN_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
168 INFO("SMB_EVTSTS_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
177 INFO("SMB_SLVDATAWR_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
180 INFO("SMB_SLVDATARD_REG=0x%x\n", regval); in iproc_dump_i2c_regs()
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/trusted-firmware-a/drivers/brcm/
A Dchimp.c95 INFO("Waiting for ChiMP handshake...\n"); in bcm_chimp_wait_handshake()
113 INFO("Got handshake from ChiMP!\n"); in bcm_chimp_wait_handshake()
220 INFO("Setting fastboot type %d entry to 0x%x\n", mode, fb_entry); in bcm_chimp_set_fastboot()
243 INFO("Transferring %d byte(s) from 0x%lx to 0x%lx\n", in bcm_chimp_load_fw_from_spi()
251 INFO("Transferred %d byte(s) from 0x%lx to 0x%lx (%lu%%)\n", in bcm_chimp_load_fw_from_spi()
318 INFO("Found chimp firmware at 0x%lx, size %lu byte(s)\n", in bcm_chimp_find_fw_in_spi()
376 INFO("Loading ChiMP firmware, addr 0x%lx, size %lu byte(s)\n", in bcm_chimp_initiate_fastboot()
385 INFO("Skip ChiMP QSPI fastboot type %d due to sideload requested\n", in bcm_chimp_initiate_fastboot()
389 INFO("Instruct ChiMP to fastboot\n"); in bcm_chimp_initiate_fastboot()
391 INFO("Fastboot mode set\n"); in bcm_chimp_initiate_fastboot()
/trusted-firmware-a/drivers/nxp/flexspi/nor/
A Dfspi.c222 INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR)); in fspi_init_ahb()
226 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); in fspi_init_ahb()
232 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); in fspi_init_ahb()
236 INFO("x_flash_cr2=0x%x\n", x_flash_cr2); in fspi_init_ahb()
426 INFO("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n", in xspi_ip_write()
468 INFO("%d ---> pv_wr_buf=0x%p\n", __LINE__, pv_wr_buf); in xspi_ip_write()
541 INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf); in xspi_write()
760 INFO("FSPI is already initialized.\n"); in fspi_init()
767 INFO("Flexspi driver: Version v1.0\n"); in fspi_init()
817 INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0)); in fspi_init()
[all …]
/trusted-firmware-a/drivers/arm/gic/v3/
A Dgic600ae_fmu.c131 INFO("GIC600-AE FMU supports %d error records\n", num_blk); in gic600_fmu_init()
226 INFO("GICD, SMID %d: %s\n", smid, gicd_sm_info[smid]); in gic600_fmu_print_sm_info()
230 INFO("SPI Collator, SMID %d: %s\n", smid, spicol_sm_info[smid]); in gic600_fmu_print_sm_info()
234 INFO("Wake Request, SMID %d: %s\n", smid, wkrqst_sm_info[smid]); in gic600_fmu_print_sm_info()
238 INFO("ITS, SMID %d: %s\n", smid, its_sm_info[smid]); in gic600_fmu_print_sm_info()
242 INFO("PPI, SMID %d: %s\n", smid, ppi_sm_info[smid]); in gic600_fmu_print_sm_info()
/trusted-firmware-a/plat/mediatek/mt8192/drivers/apusys/
A Dmtk_apusys.c19 INFO("[APUSYS] ops=0x%x\n", request_ops); in apusys_kernel_ctrl()
45 INFO("[APUSYS] reviser_ctxt=%x,%x\n", in apusys_kernel_ctrl()
48 INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n", in apusys_kernel_ctrl()
58 INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", in apusys_kernel_ctrl()
/trusted-firmware-a/plat/nxp/common/warm_reset/
A Dplat_warm_reset.c37 INFO("Not a SW(Warm) triggered reset.\n"); in is_warm_boot()
44 INFO("Warm Reset was triggered..\n"); in is_warm_boot()
46 INFO("Warm Reset was not triggered..\n"); in is_warm_boot()
112 INFO("Doing DDR Self refresh.\n"); in prep_n_execute_warm_reset()
/trusted-firmware-a/bl31/
A Dbl31_main.c139 INFO("BL31: Initialising Exception Handling Framework\n"); in bl31_main()
144 INFO("BL31: Initializing runtime services\n"); in bl31_main()
164 INFO("BL31: Initializing BL32\n"); in bl31_main()
179 INFO("BL31: Initializing RMM\n"); in bl31_main()
252 INFO("BL31: Preparing for EL3 exit to %s world\n", in bl31_prepare_next_image_entry()
/trusted-firmware-a/plat/hisilicon/hikey/
A Dhisi_mcu.c153 INFO("%s: AO_SC_SYS_CTRL2=%x\n", __func__, in hisi_mcu_start_run()
190 INFO("%s: mcu sections %d:\n", __func__, i); in hisi_mcu_load_image()
191 INFO("%s: src = 0x%x\n", in hisi_mcu_load_image()
193 INFO("%s: dst = 0x%x\n", in hisi_mcu_load_image()
195 INFO("%s: size = %d\n", __func__, head->secs[i].size); in hisi_mcu_load_image()
197 INFO("%s: [SRC 0x%x] 0x%x 0x%x 0x%x 0x%x\n", in hisi_mcu_load_image()
200 INFO("%s: [DST 0x%x] 0x%x 0x%x 0x%x 0x%x\n", in hisi_mcu_load_image()

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