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Searched refs:MPIDR_CLUSTER_MASK (Results 1 – 25 of 82) sorted by relevance

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/trusted-firmware-a/plat/mediatek/mt8173/
A Dpower_tracer.c19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
A Dscu.c14 if (mpidr & MPIDR_CLUSTER_MASK) in disable_scu()
24 if (mpidr & MPIDR_CLUSTER_MASK) in enable_scu()
/trusted-firmware-a/plat/mediatek/mt6795/
A Dpower_tracer.c19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
A Dscu.c14 if (mpidr & MPIDR_CLUSTER_MASK) in disable_scu()
24 if (mpidr & MPIDR_CLUSTER_MASK) in enable_scu()
A Dplat_pm.c66 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
254 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_affinst_on()
327 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_affinst_suspend()
/trusted-firmware-a/plat/mediatek/mt8183/aarch64/
A Dplat_helpers.S16 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
31 and x0, x0, #MPIDR_CLUSTER_MASK
/trusted-firmware-a/plat/mediatek/mt8173/aarch64/
A Dplat_helpers.S31 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
46 and x0, x0, #MPIDR_CLUSTER_MASK
/trusted-firmware-a/plat/mediatek/mt8173/drivers/spm/
A Dspm_mcdi.c307 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_enter()
358 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_leave()
408 unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
440 unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; in spm_mcdi_clear_cputop_pwrctrl_for_cluster_on()
495 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_mcdi_finish_for_on_state()
A Dspm_hotplug.c240 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_hotplug_on()
261 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_hotplug_off()
/trusted-firmware-a/plat/mediatek/mt8183/
A Dscu.c21 switch (mpidr & MPIDR_CLUSTER_MASK) { in disable_scu()
42 switch (mpidr & MPIDR_CLUSTER_MASK) { in enable_scu()
/trusted-firmware-a/plat/rockchip/common/aarch32/
A Dplat_helpers.S43 and r0, r0, #MPIDR_CLUSTER_MASK
69 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
102 and r6, r0, #MPIDR_CLUSTER_MASK
/trusted-firmware-a/plat/rockchip/common/aarch64/
A Dplat_helpers.S57 and x0, x0, #MPIDR_CLUSTER_MASK
79 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
106 and x20, x0, #MPIDR_CLUSTER_MASK
/trusted-firmware-a/plat/hisilicon/hikey960/
A Dhikey960_pm.c66 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_on()
97 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_off()
193 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend()
269 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend_finish()
/trusted-firmware-a/plat/mediatek/mt6795/aarch64/
A Dplat_helpers.S49 and x1, x1, #MPIDR_CLUSTER_MASK
91 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
/trusted-firmware-a/plat/imx/common/
A Dimx8_helpers.S72 and x0, x0, #MPIDR_CLUSTER_MASK
84 and x0, x0, #MPIDR_CLUSTER_MASK
A Dimx8_topology.c29 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/qemu/common/aarch32/
A Dplat_helpers.S35 and r0, r0, #MPIDR_CLUSTER_MASK
49 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
/trusted-firmware-a/plat/qemu/common/aarch64/
A Dplat_helpers.S34 and x0, x0, #MPIDR_CLUSTER_MASK
49 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
/trusted-firmware-a/plat/xilinx/versal/
A Dplat_versal.c12 if (mpidr & MPIDR_CLUSTER_MASK) { in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/xilinx/zynqmp/
A Dplat_zynqmp.c12 if (mpidr & MPIDR_CLUSTER_MASK) { in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/hisilicon/poplar/
A Dplat_topology.c26 if (mpidr & MPIDR_CLUSTER_MASK) in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/rockchip/common/
A Dplat_topology.c30 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/intel/soc/common/
A Dsocfpga_topology.c33 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/layerscape/common/
A Dls_topology.c19 valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); in ls_check_mpidr()
/trusted-firmware-a/plat/amlogic/common/
A Daml_topology.c40 if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) in plat_core_pos_by_mpidr()

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