/trusted-firmware-a/plat/imx/imx8qx/ |
A D | imx8qx_bl31_setup.c | 243 NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end); in imx8_partition_resources() 249 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \ in imx8_partition_resources() 262 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in imx8_partition_resources() 266 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in imx8_partition_resources() 273 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in imx8_partition_resources() 277 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in imx8_partition_resources()
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/trusted-firmware-a/plat/imx/imx8qm/ |
A D | imx8qm_bl31_setup.c | 266 NOTICE("Memreg %u 0x%" PRIx64 " -- 0x%" PRIx64 "\n", mr, start, end); in mx8_partition_resources() 272 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 ", \ in mx8_partition_resources() 285 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in mx8_partition_resources() 289 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in mx8_partition_resources() 296 ERROR("sc_rm_memreg_alloc failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in mx8_partition_resources() 300 ERROR("Memreg assign failed, 0x%" PRIx64 " -- 0x%" PRIx64 "\n", in mx8_partition_resources()
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/trusted-firmware-a/drivers/marvell/ |
A D | amb_adec.c | 50 WARN("Window %d: base address is too big 0x%" PRIx64 "\n", in amb_check_win() 53 WARN("Set the base address to 0x%" PRIx64 "\n", win->base_addr); in amb_check_win() 63 WARN("Align up the base address to 0x%" PRIx64 "\n", win->base_addr); in amb_check_win() 68 WARN("Window %d: window size is not power of 2 (0x%" PRIx64 ")\n", in amb_check_win() 71 WARN("Rounding size to 0x%" PRIx64 "\n", win->win_size); in amb_check_win()
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A D | gwin.c | 55 NOTICE("%s: Align the base address to 0x%" PRIx64 "\n", in gwin_check() 62 NOTICE("%s: Aligning window size to 0x%" PRIx64 "\n", in gwin_check() 173 printf("\tgwin %d 0x%016" PRIx64 " 0x%016" PRIx64 "\n", in dump_gwin()
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A D | iob.c | 63 printf("Align up the base address to 0x%" PRIx64 "\n", in iob_win_check() 72 printf("Aligning size to 0x%" PRIx64 "\n", win->win_size); in iob_win_check() 136 printf("iob %02d %s 0x%016" PRIx64 " 0x%016" PRIx64 "\n", in dump_iob()
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A D | io_win.c | 50 NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n", in io_win_check() 57 NOTICE("%s: Aligning size to 0x%" PRIx64 "\n", in io_win_check() 176 printf("\tio-win %d 0x%016" PRIx64 " 0x%016" PRIx64 "\n", in dump_io_win()
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A D | ccu.c | 90 printf("\tccu%d %02x 0x%016" PRIx64 " 0x%016" PRIx64 "\n", in dump_ccu() 105 NOTICE("%s: Align up the base address to 0x%" PRIx64 "\n", in ccu_win_check() 112 NOTICE("%s: Aligning size to 0x%" PRIx64 "\n", in ccu_win_check()
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/trusted-firmware-a/plat/xilinx/common/ |
A D | plat_startup.c | 175 ERROR("BL31: invalid ATF handoff structure at %" PRIx64 "\n", in fsbl_atf_handover() 180 VERBOSE("BL31: ATF handoff params at:0x%" PRIx64 ", entries:%u\n", in fsbl_atf_handover() 198 VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i, in fsbl_atf_handover() 259 VERBOSE("Setting up %s entry point to:%" PRIx64 ", el:%x\n", in fsbl_atf_handover()
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/trusted-firmware-a/services/std_svc/spmd/ |
A D | spmd_main.c | 55 ERROR("Invalid mpidr: %" PRIx64 ", returned ID: %d\n", mpidr, core_idx); in spmd_get_context_by_mpidr() 162 ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc); in spmd_init() 511 VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 in spmd_smc_handler() 512 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n", in spmd_smc_handler()
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/trusted-firmware-a/plat/common/aarch64/ |
A D | plat_common.c | 58 WARN("Spurious SDEI interrupt %u on masked PE %" PRIx64 "\n", intr, mpidr); in plat_sdei_handle_masked_trigger() 98 ERROR("exception reason=%u syndrome=0x%" PRIx64 "\n", ea_reason, syndrome); in plat_default_ea_handler()
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/trusted-firmware-a/drivers/marvell/mc_trustzone/ |
A D | mc_trustzone.c | 45 VERBOSE("%s: window size = 0x%" PRIx64 " maps to tz_size %d\n", in tz_enable_win() 55 WARN("Attempt to open MC TZ win. at 0x%" PRIx64 ", truncate to 0x%x\n", in tz_enable_win()
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/trusted-firmware-a/services/std_svc/sdei/ |
A D | sdei_main.c | 978 SDEI_LOG("< VER:%" PRIx64 "\n", ret); in sdei_smc_handler() 983 SDEI_LOG("> REG(n:%d e:%" PRIx64 " a:%" PRIx64 " f:%x m:%" PRIx64 "\n", ev_num, in sdei_smc_handler() 1012 SDEI_LOG("> COMPLETE(r:%u sta/ep:%" PRIx64 "):%lx\n", in sdei_smc_handler() 1015 SDEI_LOG("< COMPLETE:%" PRIx64 "\n", ret); in sdei_smc_handler() 1084 SDEI_LOG("> ROUTE_SET(n:%d f:%" PRIx64 " aff:%" PRIx64 ")\n", ev_num, x2, x3); in sdei_smc_handler() 1090 SDEI_LOG("> FTRS(f:%" PRIx64 ")\n", x1); in sdei_smc_handler() 1092 SDEI_LOG("< FTRS:%" PRIx64 "\n", ret); in sdei_smc_handler() 1096 SDEI_LOG("> SIGNAL(e:%d t:%" PRIx64 ")\n", ev_num, x2); in sdei_smc_handler()
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/trusted-firmware-a/common/ |
A D | fdt_wrappers.c | 407 VERBOSE("DT: Address %" PRIx64 " mapped to %" PRIx64 " with range %" PRIx64 "\n", in fdtw_xlat_hit() 418 VERBOSE("DT: child address %" PRIx64 "mapped to %" PRIx64 " in parent bus\n", in fdtw_xlat_hit() 475 INFO("DT: No translation found for address %" PRIx64 " in node %s\n", in fdtw_search_all_xlat_entries()
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/trusted-firmware-a/plat/nvidia/tegra/common/ |
A D | tegra_bl31_setup.c | 340 ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n", in bl31_check_ns_address() 351 ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base); in bl31_check_ns_address() 360 ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base); in bl31_check_ns_address()
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/trusted-firmware-a/include/lib/libc/aarch32/ |
A D | inttypes_.h | 18 #define PRIx64 "llx" /* uint64_t */ macro
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/trusted-firmware-a/include/lib/libc/aarch64/ |
A D | inttypes_.h | 18 #define PRIx64 "lx" /* uint64_t */ macro
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/trusted-firmware-a/plat/nvidia/tegra/soc/t194/ |
A D | plat_ras.c | 58 ERROR("MPIDR 0x%lx: exception reason=%u syndrome=0x%" PRIx64 "\n", in tegra194_ea_handler() 150 VERBOSE("errselr_el1:0x%x, erxfr:0x%" PRIx64 ", err_ctrl:0x%" PRIx64 "\n", in tegra194_ras_enable() 292 ERROR("\tStatus = 0x%" PRIx64 "\n", status); in tegra194_ras_node_handler()
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/trusted-firmware-a/lib/gpt_rme/ |
A D | gpt_rme.c | 449 VERBOSE("[GPT] L0 entry (BLOCK) index %u [%p]: GPI = 0x%" PRIx64 " (0x%" PRIx64 ")\n", in gpt_generate_l0_blk_desc() 610 VERBOSE("[GPT] L0 entry (TABLE) index %u [%p] ==> L1 Addr 0x%llx (0x%" PRIx64 ")\n", in gpt_generate_l0_tbl_desc() 1046 VERBOSE(" Base=0x%" PRIx64 "\n", base); in gpt_transition_pas() 1057 VERBOSE(" Base=0x%" PRIx64 "\n", base); in gpt_transition_pas() 1076 VERBOSE(" Base=0x%" PRIx64 "\n", base); in gpt_transition_pas() 1120 VERBOSE("[GPT] Granule 0x%" PRIx64 ", GPI 0x%x->0x%x\n", base, gpi, in gpt_transition_pas()
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/trusted-firmware-a/plat/common/ |
A D | plat_spmd_manifest.c | 85 VERBOSE(" load_address: 0x%" PRIx64 "\n", attr->load_address); in manifest_parse_attribute() 86 VERBOSE(" entrypoint: 0x%" PRIx64 "\n", attr->entrypoint); in manifest_parse_attribute()
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/trusted-firmware-a/plat/nxp/common/setup/ |
A D | ls_bl31_setup.c | 131 VERBOSE("Number of DRAM Regions = %" PRIx64 "\n", in bl31_early_platform_setup2() 140 VERBOSE("DRAM%d Size = %" PRIx64 "\n", i, in bl31_early_platform_setup2()
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/trusted-firmware-a/lib/bl_aux_params/ |
A D | bl_aux_params.c | 30 ERROR("Ignoring unknown BL aux parameter: 0x%" PRIx64, in bl_aux_params_parse()
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/trusted-firmware-a/services/std_svc/rmmd/ |
A D | rmmd_main.c | 136 ERROR("RMM initialisation failed 0x%" PRIx64 "\n", rc); in rmm_init() 306 ERROR(" PA: 0x%" PRIx64 ", SRC: %d, PAS: %d\n", pa, in gtsi_transition_granule() 311 ERROR(" PA: 0x%" PRIx64 ", SRC: %d, PAS: %d\n", pa, in gtsi_transition_granule()
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/trusted-firmware-a/plat/marvell/armada/a3k/common/ |
A D | a3700_ea.c | 79 " syndrome 0x%" PRIx64 " received on 0x%lx from %s\n", in plat_ea_handler()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t210/ |
A D | plat_sip_calls.c | 77 ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); in plat_sip_handler()
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/trusted-firmware-a/bl32/tsp/ |
A D | tsp_interrupt.c | 40 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n", in tsp_update_sync_sel1_intr_stats()
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