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/trusted-firmware-a/plat/amlogic/g12a/
A Dg12a_def.h20 #define AML_HDCP_RX_BASE UL(0xFFE0D000)
21 #define AML_HDCP_RX_SIZE UL(0x00002000)
23 #define AML_HDCP_TX_BASE UL(0xFFE01000)
24 #define AML_HDCP_TX_SIZE UL(0x00001000)
35 #define AML_NSDRAM0_BASE UL(0x01000000)
36 #define AML_NSDRAM0_SIZE UL(0x0F000000)
38 #define BL31_BASE UL(0x05100000)
39 #define BL31_SIZE UL(0x00100000)
52 #define AML_TZRAM_BASE UL(0xFFFA0000)
66 #define AML_GICD_BASE UL(0xFFC01000)
[all …]
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_def.h39 #define FLASH1_BASE UL(0x0c000000)
40 #define FLASH1_SIZE UL(0x04000000)
42 #define PSRAM_BASE UL(0x14000000)
43 #define PSRAM_SIZE UL(0x04000000)
45 #define VRAM_BASE UL(0x18000000)
46 #define VRAM_SIZE UL(0x02000000)
73 #define NSRAM_SIZE UL(0x10000)
85 #define TFW_NVCTR_SIZE UL(4)
87 #define NTFW_CTR_SIZE UL(4)
94 #define HU_KEY_SIZE UL(16)
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/trusted-firmware-a/plat/amlogic/gxbb/
A Dgxbb_def.h20 #define AML_NSDRAM0_BASE UL(0x01000000)
21 #define AML_NSDRAM0_SIZE UL(0x0F000000)
23 #define AML_NSDRAM1_BASE UL(0x10000000)
24 #define AML_NSDRAM1_SIZE UL(0x00100000)
26 #define BL31_BASE UL(0x10100000)
27 #define BL31_SIZE UL(0x000C0000)
40 #define AML_TZRAM_BASE UL(0xD9000000)
41 #define AML_TZRAM_SIZE UL(0x00014000)
49 #define AML_TZROM_BASE UL(0xD9040000)
61 #define AML_GICD_BASE UL(0xC4301000)
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/trusted-firmware-a/plat/amlogic/axg/
A Daxg_def.h26 #define AML_GIC_DEVICE_BASE UL(0xFFC00000)
27 #define AML_GIC_DEVICE_SIZE UL(0x00008000)
29 #define AML_NSDRAM0_BASE UL(0x01000000)
30 #define AML_NSDRAM0_SIZE UL(0x0F000000)
32 #define BL31_BASE UL(0x05100000)
33 #define BL31_SIZE UL(0x00100000)
49 #define AML_TZRAM_BASE UL(0xFFFC0000)
50 #define AML_TZRAM_SIZE UL(0x00020000)
60 #define AML_GICD_BASE UL(0xFFC01000)
61 #define AML_GICC_BASE UL(0xFFC02000)
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/trusted-firmware-a/plat/amlogic/gxl/
A Dgxl_def.h20 #define AML_NSDRAM0_BASE UL(0x01000000)
21 #define AML_NSDRAM0_SIZE UL(0x0F000000)
23 #define AML_NSDRAM1_BASE UL(0x10000000)
24 #define AML_NSDRAM1_SIZE UL(0x00100000)
26 #define BL31_BASE UL(0x05100000)
27 #define BL31_SIZE UL(0x000C0000)
40 #define AML_TZRAM_BASE UL(0xD9000000)
41 #define AML_TZRAM_SIZE UL(0x00014000)
53 #define AML_TZROM_BASE UL(0xD9040000)
65 #define AML_GICD_BASE UL(0xC4301000)
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/trusted-firmware-a/plat/arm/board/fvp_r/
A Dfvp_r_def.h29 #define FLASH1_BASE UL(0x8c000000)
30 #define FLASH1_SIZE UL(0x04000000)
32 #define PSRAM_BASE UL(0x94000000)
33 #define PSRAM_SIZE UL(0x04000000)
35 #define VRAM_BASE UL(0x98000000)
36 #define VRAM_SIZE UL(0x02000000)
50 #define NSRAM_SIZE UL(0x10000)
61 #define TFW_NVCTR_SIZE UL(4)
63 #define NTFW_CTR_SIZE UL(4)
70 #define HU_KEY_SIZE UL(16)
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/trusted-firmware-a/plat/arm/board/fvp_r/include/
A Dplatform_def.h17 .image_info.image_max_size = UL(0x3ffff000), \
89 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
91 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
127 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
138 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
139 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
140 #define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0)
162 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000)
169 # define PLATFORM_STACK_SIZE UL(0x1000)
171 # define PLATFORM_STACK_SIZE UL(0x500)
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/trusted-firmware-a/plat/arm/board/juno/include/
A Dplatform_def.h33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000)
50 #define NSRAM_BASE UL(0x2e000000)
77 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
78 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
79 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0)
179 # define PLATFORM_STACK_SIZE UL(0x440)
185 # define PLATFORM_STACK_SIZE UL(0x400)
188 # define PLATFORM_STACK_SIZE UL(0x400)
191 # define PLATFORM_STACK_SIZE UL(0x800)
193 # define PLATFORM_STACK_SIZE UL(0x400)
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/trusted-firmware-a/plat/arm/board/fvp/include/
A Dplatform_def.h64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
67 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
138 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
139 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
140 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
193 # define PLATFORM_STACK_SIZE UL(0x500)
199 # define PLATFORM_STACK_SIZE UL(0x600)
202 # define PLATFORM_STACK_SIZE UL(0x400)
204 # define PLATFORM_STACK_SIZE UL(0x800)
206 # define PLATFORM_STACK_SIZE UL(0x440)
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/trusted-firmware-a/lib/xlat_mpu/
A Dxlat_mpu_private.h42 #define PRBAR_SH_SHIFT UL(4)
43 #define PRBAR_SH_MASK UL(0x3)
44 #define PRBAR_AP_SHIFT UL(2)
45 #define PRBAR_AP_MASK UL(0x3)
46 #define PRBAR_XN_SHIFT UL(1)
47 #define PRBAR_XN_MASK UL(0x3)
48 #define PRLAR_NS_SHIFT UL(4)
54 #define PRLAR_EN_SHIFT UL(0)
57 #define MT_PERM_MASK UL(0x1)
58 #define MT_SEC_MASK UL(0x1)
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A Dxlat_mpu_core.c40 uint64_t retValue = UL(0); in prbar_attr_value()
70 uint64_t retValue = UL(0); in prlar_attr_value()
77 case UL(0): in prlar_attr_value()
80 case UL(2): in prlar_attr_value()
83 case UL(3): in prlar_attr_value()
107 uint64_t prenr_el2_value = 0UL; in mpu_map_region()
108 uint64_t prbar_attrs = 0UL; in mpu_map_region()
109 uint64_t prlar_attrs = 0UL; in mpu_map_region()
320 uint64_t mair = UL(0); in init_xlat_tables_ctx()
387 uint64_t region_n = 0UL; in clear_all_mpu_regions()
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/trusted-firmware-a/include/plat/arm/board/common/
A Dv2m_def.h15 #define V2M_OFFSET UL(0)
19 #define V2M_SYSREGS_BASE UL(0x1c010000)
20 #define V2M_SYS_ID UL(0x0)
21 #define V2M_SYS_SWITCH UL(0x4)
22 #define V2M_SYS_LED UL(0x8)
23 #define V2M_SYS_NVFLAGS UL(0x38)
24 #define V2M_SYS_NVFLAGSSET UL(0x38)
25 #define V2M_SYS_NVFLAGSCLR UL(0x3c)
26 #define V2M_SYS_CFGDATA UL(0xa0)
27 #define V2M_SYS_CFGCTRL UL(0xa4)
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/trusted-firmware-a/plat/arm/css/sgi/include/
A Dsgi_soc_css_def_v2.h19 #define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
20 #define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
28 #define SOC_CSS_UART1_BASE UL(0x0ef80000)
29 #define SOC_CSS_UART0_BASE UL(0x0ef70000)
32 #define SOC_MEMCNTRL_BASE UL(0x10000000)
33 #define SOC_MEMCNTRL_SIZE UL(0x10000000)
39 #define SOC_CSS_NIC400_BASE UL(0x0ED00000)
60 #define SOC_KEYS_BASE UL(0x0EE80000)
108 #define V2M_SYSREGS_BASE UL(0x0C010000)
130 #define V2M_FLASH0_BASE UL(0x08000000)
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/trusted-firmware-a/include/drivers/arm/
A Dcci.h13 #define SLAVE_IFACE6_OFFSET UL(0x7000)
14 #define SLAVE_IFACE5_OFFSET UL(0x6000)
15 #define SLAVE_IFACE4_OFFSET UL(0x5000)
16 #define SLAVE_IFACE3_OFFSET UL(0x4000)
17 #define SLAVE_IFACE2_OFFSET UL(0x3000)
18 #define SLAVE_IFACE1_OFFSET UL(0x2000)
19 #define SLAVE_IFACE0_OFFSET UL(0x1000)
21 (UL(0x1000) * (index)))
24 #define EVENT_SELECT7_OFFSET UL(0x80000)
25 #define EVENT_SELECT6_OFFSET UL(0x70000)
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/trusted-firmware-a/plat/arm/board/juno/
A Djuno_def.h27 #define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000)
29 #define EMMC_BASE UL(0x0c000000)
30 #define EMMC_SIZE UL(0x04000000)
32 #define PSRAM_BASE UL(0x14000000)
33 #define PSRAM_SIZE UL(0x02000000)
62 #define TRNG_BASE UL(0x7FE60000)
64 #define TRNG_STATUS UL(0x10)
65 #define TRNG_INTMASK UL(0x14)
66 #define TRNG_CONFIG UL(0x18)
67 #define TRNG_CONTROL UL(0x1C)
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/trusted-firmware-a/plat/hisilicon/hikey960/include/
A Dhi3660.h243 #define GPIO0_BASE UL(0xE8A0B000)
244 #define GPIO1_BASE UL(0xE8A0C000)
245 #define GPIO2_BASE UL(0xE8A0D000)
246 #define GPIO3_BASE UL(0xE8A0E000)
247 #define GPIO4_BASE UL(0xE8A0F000)
248 #define GPIO5_BASE UL(0xE8A10000)
249 #define GPIO6_BASE UL(0xE8A11000)
250 #define GPIO7_BASE UL(0xE8A12000)
251 #define GPIO8_BASE UL(0xE8A13000)
252 #define GPIO9_BASE UL(0xE8A14000)
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/trusted-firmware-a/plat/arm/board/rdn1edge/include/
A Dplatform_def.h19 #define PLAT_CSS_MHU_BASE UL(0x45400000)
22 #define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
23 #define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
31 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
45 #define PLAT_ARM_GICD_BASE UL(0x30000000)
46 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
47 #define PLAT_ARM_GICR_BASE UL(0x300C0000)
/trusted-firmware-a/plat/arm/board/diphda/common/include/
A Dplatform_def.h130 #define ARM_DRAM1_BASE UL(0x80000000)
131 #define ARM_DRAM1_SIZE UL(0x80000000)
146 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
147 #define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */
163 #define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */
203 #define PLAT_ARM_FIP_BASE UL(0x08131000)
207 #define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */
258 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
259 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
260 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
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/trusted-firmware-a/plat/arm/board/sgi575/include/
A Dplatform_def.h19 #define PLAT_CSS_MHU_BASE UL(0x45000000)
22 #define SGI575_DMC620_BASE0 UL(0x4e000000)
23 #define SGI575_DMC620_BASE1 UL(0x4e100000)
42 #define PLAT_ARM_GICD_BASE UL(0x30000000)
43 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
44 #define PLAT_ARM_GICR_BASE UL(0x300C0000)
/trusted-firmware-a/plat/arm/board/rde1edge/include/
A Dplatform_def.h19 #define PLAT_CSS_MHU_BASE UL(0x45400000)
22 #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
23 #define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
41 #define PLAT_ARM_GICD_BASE UL(0x30000000)
42 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
43 #define PLAT_ARM_GICR_BASE UL(0x300C0000)
/trusted-firmware-a/plat/socionext/uniphier/include/
A Dplatform_def.h31 #define UNIPHIER_BL2_OFFSET UL(0x00000000)
32 #define UNIPHIER_BL2_MAX_SIZE UL(0x00080000)
36 #define UNIPHIER_BL31_OFFSET UL(0x01000000)
37 #define UNIPHIER_BL31_MAX_SIZE UL(0x00080000)
39 #define UNIPHIER_BL32_OFFSET UL(0x01080000)
40 #define UNIPHIER_BL32_MAX_SIZE UL(0x00100000)
51 #define UNIPHIER_MEM_BASE UL(0x00000000)
/trusted-firmware-a/plat/arm/board/rdv1mc/include/
A Dplatform_def.h17 #define PLAT_CSS_MHU_BASE UL(0x45400000)
24 #define PLAT_ARM_TZC_BASE UL(0x21830000)
27 #define TZC400_OFFSET UL(0x1000000)
47 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
56 #define PLAT_ARM_GICD_BASE UL(0x30000000)
57 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
58 #define PLAT_ARM_GICR_BASE UL(0x30140000)
/trusted-firmware-a/plat/arm/board/tc/include/
A Dplatform_def.h34 #define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
72 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
208 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
209 #define SBSA_SECURE_WDOG_TIMEOUT UL(100)
217 #define PLAT_CSS_MHU_BASE UL(0x45400000)
230 #define PLAT_ARM_GICD_BASE UL(0x30000000)
231 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
232 #define PLAT_ARM_GICR_BASE UL(0x30080000)
247 #define PLAT_ARM_TZC_BASE UL(0x25000000)
250 #define TZC400_OFFSET UL(0x1000000)
[all …]
/trusted-firmware-a/plat/arm/board/rdn2/include/
A Dplatform_def.h23 #define PLAT_CSS_MHU_BASE UL(0x2A920000)
30 #define PLAT_ARM_TZC_BASE UL(0x10720000)
33 #define TZC400_OFFSET UL(0x1000000)
75 #define PLAT_ARM_GICD_BASE UL(0x30000000)
76 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
79 #define PLAT_ARM_GICR_BASE UL(0x30100000)
81 #define PLAT_ARM_GICR_BASE UL(0x301C0000)
/trusted-firmware-a/plat/arm/board/rdv1/include/
A Dplatform_def.h18 #define PLAT_CSS_MHU_BASE UL(0x45400000)
25 #define PLAT_ARM_TZC_BASE UL(0x21830000)
28 #define TZC400_OFFSET UL(0x1000000)
61 #define PLAT_ARM_GICD_BASE UL(0x30000000)
62 #define PLAT_ARM_GICC_BASE UL(0x2C000000)
63 #define PLAT_ARM_GICR_BASE UL(0x30140000)

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