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/trusted-firmware-a/plat/hisilicon/hikey/
A Dhikey_ddr.c25 data |= 0x1; in init_pll()
32 data &= ~0x007; in init_pll()
33 data |= 0x004; in init_pll()
37 data &= 0x007; in init_pll()
100 data &= ~0x7; in init_freq()
101 data |= 0x5; in init_freq()
184 data = (data & (0x7f << 8)) >> 8; in init_freq()
275 if ((data & 0x1f00) && ((data & 0x1f) == 0)) { in cat_533mhz_800mhz()
478 if ((!(data & 0x1f)) || (!(data & 0x1f00)) || in ddrx_wdet()
482 if ((!(data & 0x1f)) || (!(data & 0x1f00)) || in ddrx_wdet()
[all …]
A Dhikey_bl_common.c19 uint32_t data; in hikey_sp804_init() local
24 data &= ~3; in hikey_sp804_init()
31 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { in hikey_sp804_init()
40 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)); in hikey_sp804_init()
45 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0)); in hikey_sp804_init()
167 data = (data & 0xf8) | 0x2; in hikey_hi6553_init()
174 data = (data & 0xf8) | 0x5; in hikey_hi6553_init()
181 data = (data & 0xf8) | 0x4; in hikey_hi6553_init()
193 data = (data & 0xf8) | 0x3; in hikey_hi6553_init()
199 data = (data & 0xf8) | 0x7; in hikey_hi6553_init()
[all …]
A Dhikey_bl2_setup.c188 unsigned int data; in reset_dwmmc_clk() local
194 } while (data & PERI_CLK0_MMC0); in reset_dwmmc_clk()
199 } while (!(data & PERI_CLK0_MMC0)); in reset_dwmmc_clk()
204 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); in reset_dwmmc_clk()
205 data |= 3; in reset_dwmmc_clk()
206 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); in reset_dwmmc_clk()
209 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); in reset_dwmmc_clk()
210 data |= 1 << 3; in reset_dwmmc_clk()
211 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); in reset_dwmmc_clk()
214 } while (!(data & PERI_RST0_MMC0)); in reset_dwmmc_clk()
[all …]
/trusted-firmware-a/drivers/marvell/comphy/
A Dphy-comphy-cp110.c316 mask = data; in mvebu_cp110_comphy_is_pll_locked()
317 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_is_pll_locked()
817 mask = data; in mvebu_cp110_comphy_sgmii_power_on()
947 data = 0x0U; in mvebu_cp110_comphy_xfi_power_on()
1209 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1210 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_xfi_power_on()
1229 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1434 data = 0; in mvebu_cp110_comphy_pcie_power_on()
1559 data = 0; in mvebu_cp110_comphy_pcie_power_on()
1735 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_pcie_power_on()
[all …]
A Dphy-comphy-3700.c374 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_on() local
411 data = 0; in mvebu_a3700_comphy_sgmii_power_on()
451 data = 0; in mvebu_a3700_comphy_sgmii_power_on()
520 data = 0x0; in mvebu_a3700_comphy_sgmii_power_on()
595 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_off() local
600 mask = data; in mvebu_a3700_comphy_sgmii_power_off()
753 data = 0U; in mvebu_a3700_comphy_usb3_power_on()
788 data); in mvebu_a3700_comphy_usb3_power_on()
813 uint32_t mask, data; in mvebu_a3700_comphy_pcie_power_on() local
876 data = 0U; in mvebu_a3700_comphy_pcie_power_on()
[all …]
A Dphy-comphy-common.h129 uint32_t data; in polling_with_timeout() local
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
137 } while (data != val && --usec_timeout > 0); in polling_with_timeout()
140 return data; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data); in reg_set()
155 static inline void __unused reg_set16(uintptr_t addr, uint16_t data, in reg_set16() argument
160 addr, data, mask); in reg_set16()
[all …]
/trusted-firmware-a/plat/intel/soc/agilex/soc/
A Dagilex_memory_controller.c91 uint32_t data; in clear_emif() local
112 uint32_t data; in mem_calibration() local
211 act_to_act = ACT_TO_ACT(data); in configure_ddr_sched_ctrl_regs()
212 t_rcd = ACT_TO_RDWR(data); in configure_ddr_sched_ctrl_regs()
216 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
221 t_rtp = RD_TO_PCH(data); in configure_ddr_sched_ctrl_regs()
228 t_rp = PCH_TO_VALID(data); in configure_ddr_sched_ctrl_regs()
306 uint32_t data; in get_physical_dram_size() local
339 uint32_t data; in configure_hmc_adaptor_regs() local
360 if (data < AGX_DDR_SIZE) in configure_hmc_adaptor_regs()
[all …]
/trusted-firmware-a/plat/common/
A Dubsan.c114 print_loc(__func__, &data->loc); in __ubsan_handle_type_mismatch_abort()
121 print_loc(__func__, &data->loc); in __ubsan_handle_type_mismatch_v1_abort()
129 print_loc(__func__, &data->loc); in __ubsan_handle_add_overflow_abort()
137 print_loc(__func__, &data->loc); in __ubsan_handle_sub_overflow_abort()
145 print_loc(__func__, &data->loc); in __ubsan_handle_mul_overflow_abort()
152 print_loc(__func__, &data->loc); in __ubsan_handle_negate_overflow_abort()
159 print_loc(__func__, &data->loc); in __ubsan_handle_pointer_overflow_abort()
167 print_loc(__func__, &data->loc); in __ubsan_handle_divrem_overflow_abort()
175 print_loc(__func__, &data->loc); in __ubsan_handle_shift_out_of_bounds_abort()
182 print_loc(__func__, &data->loc); in __ubsan_handle_out_of_bounds_abort()
[all …]
/trusted-firmware-a/plat/intel/soc/stratix10/soc/
A Ds10_memory_controller.c95 uint32_t data; in clear_emif() local
116 uint32_t data; in mem_calibration() local
240 act_to_act = ACT_TO_ACT(data); in configure_ddr_sched_ctrl_regs()
241 t_rcd = ACT_TO_RDWR(data); in configure_ddr_sched_ctrl_regs()
245 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
246 bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data); in configure_ddr_sched_ctrl_regs()
250 t_rtp = RD_TO_PCH(data); in configure_ddr_sched_ctrl_regs()
253 wr_to_rd = CALTIMING3_WR_TO_RD(data); in configure_ddr_sched_ctrl_regs()
257 t_rp = PCH_TO_VALID(data); in configure_ddr_sched_ctrl_regs()
335 uint32_t data; in get_physical_dram_size() local
[all …]
/trusted-firmware-a/plat/brcm/board/common/
A Dplatform_common.c16 uint32_t data; in boot_source_get() local
19 data = FORCE_BOOTSOURCE; in boot_source_get()
23 if (data & BOOT_SOURCE_SOFT_ENABLE_MASK) { in boot_source_get()
24 data >>= BOOT_SOURCE_SOFT_DATA_OFFSET; in boot_source_get()
33 data = 0; in boot_source_get()
35 data |= 0x1; in boot_source_get()
37 data |= 0x2; in boot_source_get()
39 data |= 0x4; in boot_source_get()
59 data &= BOOT_SOURCE_MASK; in boot_source_get()
62 data << BOOT_SOURCE_SOFT_DATA_OFFSET); in boot_source_get()
[all …]
/trusted-firmware-a/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c111 unsigned int data, mask; in hikey960_ufs_reset() local
129 } while ((data & PERI_UFS_BIT) == 0); in hikey960_ufs_reset()
140 data = SC_DIV_UFSPHY_CFG(3); in hikey960_ufs_reset()
144 data |= 0x39; in hikey960_ufs_reset()
167 } while (data & PERI_UFS_BIT); in hikey960_ufs_reset()
237 unsigned int data = 0; in bl1_plat_set_ep_info() local
254 data = read_cpacr_el1(); in bl1_plat_set_ep_info()
256 data |= 3 << 20; in bl1_plat_set_ep_info()
257 write_cpacr_el1(data); in bl1_plat_set_ep_info()
258 data = read_cpacr_el1(); in bl1_plat_set_ep_info()
[all …]
/trusted-firmware-a/plat/brcm/board/stingray/driver/
A Dswreg.c30 #define BSTI_CMD(sb, op, pa, ra, ta, data) \ argument
33 (((ta) & 0x3) << 16) | (data))
45 #define UPDATE_POS_EDGE(data, set) ((data) | ((set) << 1)) argument
144 uint32_t data; in swreg_poll() local
191 *data &= BSTI_REG_DATA_MASK; in read_swreg_config()
226 uint32_t data; in dump_swreg_firmware() local
245 uint32_t data = IHOST_VDDC_DATA; in set_swreg() local
269 data = DDR_CORE_DATA; in set_swreg()
272 UPDATE_POS_EDGE(data, 1)); in set_swreg()
277 UPDATE_POS_EDGE(data, 0)); in set_swreg()
[all …]
/trusted-firmware-a/drivers/nxp/auth/tbbr/
A Dtbbr_cot.c159 .data = {
166 .data = {
202 .data = {
234 .data = {
241 .data = {
305 .data = {
337 .data = {
344 .data = {
351 .data = {
358 .data = {
[all …]
/trusted-firmware-a/drivers/auth/dualroot/
A Dcot.c153 .data = {
160 .data = {
167 .data = {
174 .data = {
276 .data = {
310 .data = {
343 .data = {
392 .data = {
425 .data = {
432 .data = {
[all …]
/trusted-firmware-a/drivers/auth/tbbr/
A Dtbbr_cot_bl2.c113 .data = {
120 .data = {
155 .data = {
187 .data = {
236 .data = {
268 .data = {
275 .data = {
339 .data = {
371 .data = {
378 .data = {
[all …]
A Dtbbr_cot_bl1.c35 .data = &raw_data,
56 .data = &raw_data
63 .data = {
70 .data = {
77 .data = {
95 .data = &raw_data,
112 .data = &raw_data,
129 .data = &raw_data,
146 .data = &raw_data,
161 .data = &raw_data,
/trusted-firmware-a/plat/mediatek/mt8183/drivers/sspm/
A Dsspm.c31 int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len) in sspm_mbox_read() argument
38 if (data) in sspm_mbox_read()
39 memcpy_from_sspm(data, in sspm_mbox_read()
46 int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len) in sspm_mbox_write() argument
53 if (data) in sspm_mbox_write()
55 data, in sspm_mbox_write()
79 int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data) in sspm_ipi_send_non_blocking() argument
89 data, in sspm_ipi_send_non_blocking()
95 data, in sspm_ipi_send_non_blocking()
112 memcpy_from_sspm(data, in sspm_ipi_recv_non_blocking()
[all …]
/trusted-firmware-a/drivers/synopsys/emmc/
A Ddw_mmc.c143 unsigned int data; in dw_update_clk() local
150 if ((data & CMD_START) == 0) in dw_update_clk()
153 assert((data & INT_HLE) == 0); in dw_update_clk()
159 unsigned int data; in dw_set_clk() local
191 unsigned int data; in dw_init() local
201 } while (data); in dw_init()
216 } while (data & BMOD_SWRESET); in dw_init()
218 data |= BMOD_ENABLE | BMOD_FB; in dw_init()
301 if (data & err_mask) in dw_send_cmd()
303 if (data & INT_DTO) in dw_send_cmd()
[all …]
/trusted-firmware-a/drivers/marvell/mochi/
A Dcp110_setup.c163 uint32_t data; in cp110_errata_wa_init() local
255 uint32_t index, data; in cp110_axi_attr_init() local
275 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; in cp110_axi_attr_init()
276 data |= (CACHE_ATTR_WRITE_ALLOC | in cp110_axi_attr_init()
280 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; in cp110_axi_attr_init()
281 data |= (CACHE_ATTR_READ_ALLOC | in cp110_axi_attr_init()
286 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; in cp110_axi_attr_init()
287 data |= DOMAIN_OUTER_SHAREABLE << in cp110_axi_attr_init()
290 data |= DOMAIN_OUTER_SHAREABLE << in cp110_axi_attr_init()
301 data |= (CACHE_ATTR_WRITE_ALLOC | in cp110_axi_attr_init()
[all …]
A Dapn806_setup.c194 uint32_t index, data; in apn806_axi_attr_init() local
212 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); in apn806_axi_attr_init()
213 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; in apn806_axi_attr_init()
214 data |= (CACHE_ATTR_WRITE_ALLOC | in apn806_axi_attr_init()
218 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; in apn806_axi_attr_init()
219 data |= (CACHE_ATTR_READ_ALLOC | in apn806_axi_attr_init()
224 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; in apn806_axi_attr_init()
225 data |= DOMAIN_OUTER_SHAREABLE << in apn806_axi_attr_init()
227 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; in apn806_axi_attr_init()
228 data |= DOMAIN_OUTER_SHAREABLE << in apn806_axi_attr_init()
[all …]
/trusted-firmware-a/tools/amlogic/
A Ddoimage.c25 static inline int fdwrite(int fd, uint8_t *data, size_t len) in fdwrite() argument
32 nr = write(fd, data + l, len - l); in fdwrite()
48 uint32_t data; in main() local
68 data = htole32(BL31_MAGIC); in main()
69 if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) in main()
73 data = htole32(BL31_LOADADDR); in main()
74 if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) in main()
/trusted-firmware-a/drivers/ufs/
A Dufs.c35 unsigned int data; in ufshc_send_uic_cmd() local
59 unsigned int data; in ufshc_dme_get() local
100 unsigned int data; in ufshc_dme_set() local
128 unsigned int data; in ufshc_hce_enable() local
151 unsigned int data; in ufshc_reset() local
183 int data, result; in ufshc_link_startup() local
209 unsigned int data; in get_empty_slot() local
216 data = data >> 1; in get_empty_slot()
448 unsigned int data; in ufs_send_request() local
803 if (data == 1) { in ufs_init()
[all …]
/trusted-firmware-a/tools/cert_create/src/
A Dsha.c20 unsigned char data[BUFFER_SIZE]; in sha_file() local
35 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
36 SHA384_Update(&sha512Context, data, bytes); in sha_file()
41 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
42 SHA512_Update(&sha512Context, data, bytes); in sha_file()
47 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
48 SHA256_Update(&shaContext, data, bytes); in sha_file()
/trusted-firmware-a/drivers/synopsys/ufs/
A Ddw_ufs.c20 unsigned int data; in dwufs_phy_init() local
65 result = ufshc_dme_get(VS_MPHY_DISABLE_OFFSET, 0, &data); in dwufs_phy_init()
87 assert((result == 0) && (data == 0)); in dwufs_phy_init()
99 unsigned int data, tx_lanes, rx_lanes; in dwufs_phy_set_pwr_mode() local
117 result = ufshc_dme_get(PA_TACTIVATE_OFFSET, 0, &data); in dwufs_phy_set_pwr_mode()
119 if (data < 7) { in dwufs_phy_set_pwr_mode()
174 data = mmio_read_32(base + IS); in dwufs_phy_set_pwr_mode()
175 } while ((data & UFS_INT_UPMS) == 0); in dwufs_phy_set_pwr_mode()
177 data = mmio_read_32(base + HCS); in dwufs_phy_set_pwr_mode()
178 if ((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL) in dwufs_phy_set_pwr_mode()
[all …]
/trusted-firmware-a/drivers/rpi3/mailbox/
A Drpi3_mbox.c24 uint32_t st, data; in rpi3_vc_mailbox_request_send() local
67 data = mmio_read_32(RPI3_MBOX_BASE + RPI3_MBOX0_READ_OFFSET); in rpi3_vc_mailbox_request_send()
69 if ((data & RPI3_CHANNEL_MASK) != RPI3_CHANNEL_ARM_TO_VC) { in rpi3_vc_mailbox_request_send()
70 ERROR("rpi3: mbox: Wrong channel: 0x%08x\n", data); in rpi3_vc_mailbox_request_send()
74 resp_addr = (uintptr_t)(data & ~RPI3_CHANNEL_MASK); in rpi3_vc_mailbox_request_send()
76 ERROR("rpi3: mbox: Unexpected address: 0x%08x\n", data); in rpi3_vc_mailbox_request_send()

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