/trusted-firmware-a/plat/amlogic/axg/ |
A D | axg_pm.c | 47 u_register_t mpidr = read_mpidr_el1(); in axg_system_reset() 68 u_register_t mpidr = read_mpidr_el1(); in axg_system_off() 108 axg_pm_set_reset_addr(read_mpidr_el1(), 0); in axg_pwr_domain_on_finish() 113 u_register_t mpidr = read_mpidr_el1(); in axg_pwr_domain_off() 142 axg_pm_reset(read_mpidr_el1(), 0); in axg_pwr_domain_pwr_down_wfi()
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/trusted-firmware-a/plat/amlogic/g12a/ |
A D | g12a_pm.c | 50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset() 81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off() 130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish() 149 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_off() 166 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_pwr_down_wfi()
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/trusted-firmware-a/plat/amlogic/gxl/ |
A D | gxl_pm.c | 50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset() 81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off() 130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish() 149 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_off() 165 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_pwr_down_wfi()
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/trusted-firmware-a/drivers/nxp/interconnect/ |
A D | ls_ccn.c | 18 ccn_enter_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency() 30 ccn_exit_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
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A D | ls_cci.c | 25 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency() 37 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
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/trusted-firmware-a/plat/amlogic/gxbb/ |
A D | gxbb_pm.c | 77 gxbb_program_mailbox(read_mpidr_el1(), 0); in gxbb_system_off() 114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish() 132 u_register_t mpidr = read_mpidr_el1(); in gxbb_pwr_domain_off() 152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi()
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/trusted-firmware-a/plat/brcm/common/ |
A D | brcm_ccn.c | 30 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_enter_coherency() 35 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_exit_coherency()
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/trusted-firmware-a/plat/socionext/synquacer/ |
A D | sq_ccn.c | 36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency() 44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
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/trusted-firmware-a/plat/marvell/armada/common/ |
A D | marvell_cci.c | 42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency() 51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
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/trusted-firmware-a/plat/arm/common/ |
A D | arm_cci.c | 41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency() 49 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
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A D | arm_ccn.c | 48 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency() 56 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
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/trusted-firmware-a/plat/arm/board/fvp/ |
A D | fvp_pm.c | 54 uint64_t mpidr = read_mpidr_el1(); in fvp_cluster_pwrdwn_common() 110 mpidr = read_mpidr_el1(); in fvp_power_domain_on_finish_common() 218 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_off() 246 mpidr = read_mpidr_el1(); in fvp_pwr_domain_suspend() 271 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_suspend()
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/trusted-firmware-a/plat/hisilicon/hikey960/ |
A D | hikey960_pm.c | 86 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish() 94 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_off() 111 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_off() 190 u_register_t mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend() 266 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend_finish()
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/trusted-firmware-a/plat/renesas/common/ |
A D | plat_pm.c | 79 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish() 97 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_off() 115 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend() 181 uint64_t cpu = read_mpidr_el1() & 0x0000ffff; in rcar_system_off() 274 unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU; in rcar_get_sys_suspend_power_state()
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/trusted-firmware-a/plat/socionext/uniphier/ |
A D | uniphier_cci.c | 27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable() 32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
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/trusted-firmware-a/plat/mediatek/mt6795/ |
A D | plat_pm.c | 282 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_off() 317 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend() 363 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_on_finish() 391 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend_finish()
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/trusted-firmware-a/plat/imx/imx8m/ |
A D | imx8m_psci_common.c | 60 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off() 105 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend() 127 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
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/trusted-firmware-a/services/std_svc/sdei/ |
A D | sdei_main.c | 80 SDEI_LOG("Private events initialized on %lx\n", read_mpidr_el1()); in sdei_cpu_on_init() 91 SDEI_LOG("Events masked on %lx\n", read_mpidr_el1()); in sdei_cpu_wakeup_init() 376 mpidr = read_mpidr_el1(); in sdei_event_register() 1002 SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1()); in sdei_smc_handler() 1013 (unsigned int) resume, x1, read_mpidr_el1()); in sdei_smc_handler() 1048 SDEI_LOG("> UNMASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler() 1054 SDEI_LOG("> MASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler() 1072 SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler() 1078 SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler()
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/trusted-firmware-a/plat/imx/imx8m/imx8mq/ |
A D | imx8mq_psci.c | 45 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend() 71 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
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/trusted-firmware-a/plat/brcm/board/stingray/src/ |
A D | brcm_pm_ops.c | 103 uint64_t mpidr = read_mpidr_el1(); in brcm_power_down_common() 154 scpi_set_brcm_power_state(read_mpidr_el1(), in brcm_scp_suspend() 172 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); in brcm_pwr_domain_off()
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/trusted-firmware-a/plat/arm/css/common/ |
A D | css_topology.c | 26 assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0); in plat_core_pos_by_mpidr()
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/trusted-firmware-a/plat/imx/imx8qx/ |
A D | imx8qx_psci.c | 102 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off() 113 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend() 166 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
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/trusted-firmware-a/plat/imx/imx8qm/ |
A D | imx8qm_psci.c | 105 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_on_finish() 116 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off() 135 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend() 211 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
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/trusted-firmware-a/plat/mediatek/mt8173/ |
A D | plat_pm.c | 293 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_off() 324 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend() 374 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_on_finish() 404 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend_finish()
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/trusted-firmware-a/drivers/nxp/pmu/ |
A D | pmu.c | 26 | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in enable_timer_base_to_cluster()
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