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Searched refs:read_mpidr_el1 (Results 1 – 25 of 64) sorted by relevance

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/trusted-firmware-a/plat/amlogic/axg/
A Daxg_pm.c47 u_register_t mpidr = read_mpidr_el1(); in axg_system_reset()
68 u_register_t mpidr = read_mpidr_el1(); in axg_system_off()
108 axg_pm_set_reset_addr(read_mpidr_el1(), 0); in axg_pwr_domain_on_finish()
113 u_register_t mpidr = read_mpidr_el1(); in axg_pwr_domain_off()
142 axg_pm_reset(read_mpidr_el1(), 0); in axg_pwr_domain_pwr_down_wfi()
/trusted-firmware-a/plat/amlogic/g12a/
A Dg12a_pm.c50 u_register_t mpidr = read_mpidr_el1(); in g12a_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in g12a_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in g12a_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_off()
166 u_register_t mpidr = read_mpidr_el1(); in g12a_pwr_domain_pwr_down_wfi()
/trusted-firmware-a/plat/amlogic/gxl/
A Dgxl_pm.c50 u_register_t mpidr = read_mpidr_el1(); in gxl_system_reset()
81 u_register_t mpidr = read_mpidr_el1(); in gxl_system_off()
130 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxl_pwr_domain_on_finish()
149 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_off()
165 u_register_t mpidr = read_mpidr_el1(); in gxl_pwr_domain_pwr_down_wfi()
/trusted-firmware-a/drivers/nxp/interconnect/
A Dls_ccn.c18 ccn_enter_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
30 ccn_exit_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
A Dls_cci.c25 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
37 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
/trusted-firmware-a/plat/amlogic/gxbb/
A Dgxbb_pm.c77 gxbb_program_mailbox(read_mpidr_el1(), 0); in gxbb_system_off()
114 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_on_finish()
132 u_register_t mpidr = read_mpidr_el1(); in gxbb_pwr_domain_off()
152 unsigned int core = plat_calc_core_pos(read_mpidr_el1()); in gxbb_pwr_domain_pwr_down_wfi()
/trusted-firmware-a/plat/brcm/common/
A Dbrcm_ccn.c30 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_enter_coherency()
35 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_exit_coherency()
/trusted-firmware-a/plat/socionext/synquacer/
A Dsq_ccn.c36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency()
44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
/trusted-firmware-a/plat/marvell/armada/common/
A Dmarvell_cci.c42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
/trusted-firmware-a/plat/arm/common/
A Darm_cci.c41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
49 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
A Darm_ccn.c48 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
56 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
/trusted-firmware-a/plat/arm/board/fvp/
A Dfvp_pm.c54 uint64_t mpidr = read_mpidr_el1(); in fvp_cluster_pwrdwn_common()
110 mpidr = read_mpidr_el1(); in fvp_power_domain_on_finish_common()
218 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_off()
246 mpidr = read_mpidr_el1(); in fvp_pwr_domain_suspend()
271 fvp_pwrc_write_ppoffr(read_mpidr_el1()); in fvp_pwr_domain_suspend()
/trusted-firmware-a/plat/hisilicon/hikey960/
A Dhikey960_pm.c86 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish()
94 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_off()
111 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_off()
190 u_register_t mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend()
266 unsigned long mpidr = read_mpidr_el1(); in hikey960_pwr_domain_suspend_finish()
/trusted-firmware-a/plat/renesas/common/
A Dplat_pm.c79 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_on_finish()
97 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_off()
115 unsigned long mpidr = read_mpidr_el1(); in rcar_pwr_domain_suspend()
181 uint64_t cpu = read_mpidr_el1() & 0x0000ffff; in rcar_system_off()
274 unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU; in rcar_get_sys_suspend_power_state()
/trusted-firmware-a/plat/socionext/uniphier/
A Duniphier_cci.c27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
/trusted-firmware-a/plat/mediatek/mt6795/
A Dplat_pm.c282 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_off()
317 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend()
363 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_on_finish()
391 unsigned long mpidr = read_mpidr_el1(); in plat_affinst_suspend_finish()
/trusted-firmware-a/plat/imx/imx8m/
A Dimx8m_psci_common.c60 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
105 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
127 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/trusted-firmware-a/services/std_svc/sdei/
A Dsdei_main.c80 SDEI_LOG("Private events initialized on %lx\n", read_mpidr_el1()); in sdei_cpu_on_init()
91 SDEI_LOG("Events masked on %lx\n", read_mpidr_el1()); in sdei_cpu_wakeup_init()
376 mpidr = read_mpidr_el1(); in sdei_event_register()
1002 SDEI_LOG("> CTX(p:%d):%lx\n", (int) x1, read_mpidr_el1()); in sdei_smc_handler()
1013 (unsigned int) resume, x1, read_mpidr_el1()); in sdei_smc_handler()
1048 SDEI_LOG("> UNMASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1054 SDEI_LOG("> MASK:%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1072 SDEI_LOG("> S_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler()
1078 SDEI_LOG("> P_RESET():%lx\n", read_mpidr_el1()); in sdei_smc_handler()
/trusted-firmware-a/plat/imx/imx8m/imx8mq/
A Dimx8mq_psci.c45 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
71 uint64_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/trusted-firmware-a/plat/brcm/board/stingray/src/
A Dbrcm_pm_ops.c103 uint64_t mpidr = read_mpidr_el1(); in brcm_power_down_common()
154 scpi_set_brcm_power_state(read_mpidr_el1(), in brcm_scp_suspend()
172 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); in brcm_pwr_domain_off()
/trusted-firmware-a/plat/arm/css/common/
A Dcss_topology.c26 assert((read_mpidr_el1() & MPIDR_MT_MASK) != 0); in plat_core_pos_by_mpidr()
/trusted-firmware-a/plat/imx/imx8qx/
A Dimx8qx_psci.c102 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
113 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
166 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/trusted-firmware-a/plat/imx/imx8qm/
A Dimx8qm_psci.c105 uint64_t mpidr = read_mpidr_el1(); in imx_pwr_domain_on_finish()
116 u_register_t mpidr = read_mpidr_el1(); in imx_pwr_domain_off()
135 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend()
211 u_register_t mpidr = read_mpidr_el1(); in imx_domain_suspend_finish()
/trusted-firmware-a/plat/mediatek/mt8173/
A Dplat_pm.c293 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_off()
324 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend()
374 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_on_finish()
404 unsigned long mpidr = read_mpidr_el1(); in plat_power_domain_suspend_finish()
/trusted-firmware-a/drivers/nxp/pmu/
A Dpmu.c26 | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in enable_timer_base_to_cluster()

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