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Searched refs:uint32_t (Results 1 – 25 of 1149) sorted by relevance

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/trusted-firmware-a/drivers/renesas/common/emmc/
A Demmc_hal.h125 (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
181 (uint32_t)HAL_MEMCARD_COMMAND_APP,
250 (uint32_t)HAL_MEMCARD_COMMAND_APP,
305 (uint32_t)HAL_MEMCARD_COMMAND_APP,
318 (uint32_t)HAL_MEMCARD_COMMAND_APP,
438 (uint32_t)HAL_MEMCARD_COMMAND_APP,
452 (uint32_t)HAL_MEMCARD_COMMAND_APP,
510 uint32_t api_version;
513 uint32_t max_block_count;
516 uint32_t max_clock_freq;
[all …]
/trusted-firmware-a/plat/intel/soc/common/include/
A Dsocfpga_handoff.h22 uint32_t header_magic;
23 uint32_t header_device;
54 uint32_t clock_magic;
55 uint32_t clock_length;
88 uint32_t fpga_clk_hz;
90 uint32_t clock_magic;
91 uint32_t clock_length;
111 uint32_t per_pll_pllm;
121 uint32_t fpga_clk_hz;
125 uint32_t misc_magic;
[all …]
/trusted-firmware-a/plat/xilinx/versal/pm_service/
A Dpm_api_sys.h33 uint32_t qos, uint32_t ack, uint32_t flag);
36 uint32_t latency, uint32_t qos,
51 uint32_t value, uint32_t flag);
53 uint32_t *value, uint32_t flag);
69 uint32_t value, uint32_t flag);
71 uint32_t *value, uint32_t flag);
81 uint32_t arg1, uint32_t arg2, uint32_t *value,
83 enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
84 uint32_t arg3, uint32_t *data, uint32_t flag);
93 uint32_t *result, uint32_t flag);
[all …]
A Dpm_api_sys.c248 uint32_t qos, uint32_t ack, uint32_t flag) in pm_request_device()
290 uint32_t latency, uint32_t qos, in pm_set_requirement()
473 uint32_t value, uint32_t flag) in pm_pinctrl_set_pin_param()
495 uint32_t *value, uint32_t flag) in pm_pinctrl_get_pin_param()
680 uint32_t value, uint32_t flag) in pm_pll_set_param()
702 uint32_t *value, uint32_t flag) in pm_pll_get_param()
819 enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2, in pm_query_data()
820 uint32_t arg3, uint32_t *data, uint32_t flag) in pm_query_data()
863 uint32_t arg1, uint32_t arg2, uint32_t *value, in pm_api_ioctl()
1055 uint32_t *result, uint32_t flag) in pm_get_op_characteristic()
[all …]
/trusted-firmware-a/include/drivers/st/
A Dstm32mp1_ddr.h38 uint32_t mstr;
43 uint32_t pwrctl;
44 uint32_t pwrtmg;
58 uint32_t dbg0;
59 uint32_t dbg1;
62 uint32_t pccfg;
117 uint32_t dcr;
133 uint32_t mr0;
134 uint32_t mr1;
135 uint32_t mr2;
[all …]
A Dstm32mp1_ddr_regs.h14 uint32_t mstr ; /* 0x0 Master */
20 uint32_t reserved01c; /* 0x1c */
31 uint32_t reserved05C;
45 uint32_t reserved0e8;
46 uint32_t reserved0ec;
69 uint32_t reserved19c;
73 uint32_t reserved1ac;
96 uint32_t reserved258;
98 uint32_t reserved260;
100 uint32_t reserved268;
[all …]
A Dbsec.h176 uint32_t bsec_shadow_register(uint32_t otp);
177 uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
178 uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
179 uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
180 uint32_t bsec_permanent_lock_otp(uint32_t otp);
182 uint32_t bsec_write_debug_conf(uint32_t val);
184 uint32_t bsec_write_feature_conf(uint32_t val);
185 uint32_t bsec_read_feature_conf(uint32_t *val);
200 uint32_t bsec_otp_lock(uint32_t service, uint32_t value);
202 uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
[all …]
/trusted-firmware-a/plat/mediatek/mt8173/drivers/pmic/
A Dpmic_wrap_init.h13 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
14 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
28 uint32_t mux_sel;
29 uint32_t wrap_en;
30 uint32_t dio_en;
31 uint32_t sidly;
32 uint32_t rddmy;
49 uint32_t man_en;
50 uint32_t man_cmd;
68 uint32_t int_en;
[all …]
/trusted-firmware-a/plat/mediatek/mt6795/include/
A Dmcucfg.h17 uint32_t mem_delsel0;
18 uint32_t mem_delsel1;
25 uint32_t rv_addr_lw;
26 uint32_t rv_addr_hw;
37 uint32_t mp1_cpucfg;
55 uint32_t pc_lw;
56 uint32_t pc_hw;
64 uint32_t dfd_ctrl;
65 uint32_t dfd_cnt_l;
66 uint32_t dfd_cnt_h;
[all …]
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/include/
A Dmce_private.h222 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
226 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
228 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
229 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data);
230 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
231 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
243 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value);
245 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
251 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
252 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
[all …]
/trusted-firmware-a/plat/mediatek/mt8173/include/
A Dmcucfg.h16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
24 uint32_t rv_addr_lw;
25 uint32_t rv_addr_hw;
36 uint32_t mp1_cpucfg;
54 uint32_t pc_lw;
55 uint32_t pc_hw;
63 uint32_t dfd_ctrl;
64 uint32_t dfd_cnt_l;
65 uint32_t dfd_cnt_h;
[all …]
/trusted-firmware-a/plat/mediatek/mt8183/include/
A Dmcucfg.h16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
21 uint32_t mp0_axi_config; /* 0x2C */
28 uint32_t mp0_rw_rsvd0; /* 0x6C */
29 uint32_t mp0_rw_rsvd1; /* 0x70 */
30 uint32_t mp0_ro_rsvd; /* 0x74 */
31 uint32_t reserved0_0; /* 0x78 */
34 uint32_t reserved0_1; /* 0x84 */
46 uint32_t dfd_cnt_l; /* 0x494 */
47 uint32_t dfd_cnt_h; /* 0x498 */
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/D3/
A Dpfc_init_d3.c176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
316 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
[all …]
/trusted-firmware-a/plat/rockchip/rk3399/drivers/dram/
A Ddram_spec_timing.h63 uint32_t mhz;
76 uint32_t trcd;
80 uint32_t trp;
81 uint32_t twr;
84 uint32_t trc;
98 uint32_t txp;
167 uint32_t al;
168 uint32_t cl;
170 uint32_t bl;
188 uint32_t bl;
[all …]
/trusted-firmware-a/plat/imx/common/include/
A Dimx_snvs.h15 uint32_t hplr;
16 uint32_t hpcomr;
17 uint32_t hpcr;
18 uint32_t hpsicr;
19 uint32_t hpsvcr;
20 uint32_t hpsr;
21 uint32_t hpsvsr;
23 uint32_t hphacr;
28 uint32_t lplr;
29 uint32_t lpcr;
[all …]
/trusted-firmware-a/include/drivers/nxp/auth/csf_hdr_parser/
A Dcsf_hdr.h31 uint32_t uid_flag;
47 uint32_t ie_key_sel;
104 uint32_t uid_flag;
105 uint32_t fsl_uid_0;
106 uint32_t oem_uid_0;
108 uint32_t fsl_uid_1;
109 uint32_t oem_uid_1;
113 uint32_t ie_flag;
114 uint32_t ie_key_sel;
125 uint32_t key_len;
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/M3N/
A Dpfc_init_m3n.c175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
283 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
289 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
313 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
314 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
573 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/H3/
A Dpfc_init_h3_v2.c173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
279 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
280 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
281 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
287 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
311 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
312 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
571 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
[all …]
A Dpfc_init_h3_v1.c171 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
172 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
173 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
277 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
278 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
279 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
285 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
466 #define MOD_SEL0_FM_A ((uint32_t)0U << 11U)
467 #define MOD_SEL0_FM_B ((uint32_t)1U << 11U)
554 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2H/
A Dpfc_init_g2h.c175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
283 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
289 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
313 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
314 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
573 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2N/
A Dpfc_init_g2n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
573 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
[all …]
/trusted-firmware-a/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.c42 uint32_t TMRD;
43 uint32_t TRFC;
44 uint32_t TRP;
45 uint32_t TRTW;
46 uint32_t TAL;
47 uint32_t TCL;
50 uint32_t TRC;
54 uint32_t TWR;
57 uint32_t TXP;
216 static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words) in ddr_copy()
[all …]
/trusted-firmware-a/drivers/renesas/rcar/pfc/M3/
A Dpfc_init_m3.c176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
615 uint32_t reg; in start_rtdma0_descriptor()
652 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
654 uint32_t prr; in pfc_reg_write()
[all …]
/trusted-firmware-a/drivers/renesas/rzg/pfc/G2M/
A Dpfc_init_g2m.c176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
615 uint32_t reg; in start_rtdma0_descriptor()
652 static void pfc_reg_write(uint32_t addr, uint32_t data) in pfc_reg_write()
654 uint32_t prr; in pfc_reg_write()
[all …]
/trusted-firmware-a/include/drivers/brcm/emmc/
A Demmc_chal_sd.h154 uint32_t rdWaiting;
156 uint32_t wakeupIn;
159 uint32_t gapInt;
160 uint32_t readWait;
161 uint32_t led;
170 uint32_t sdBase, uint32_t hostBase);
172 uint32_t retry, uint32_t boundary,
173 uint32_t blkSize, uint32_t dma);
179 uint32_t arg, uint32_t options);
182 uint32_t div_ctrl_setting, uint32_t on);
[all …]

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