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Searched refs:uint64_t (Results 1 – 25 of 508) sorted by relevance

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/trusted-firmware-a/plat/qti/qtiseclib/inc/
A Dqtiseclib_defs.h43 uint64_t x0;
44 uint64_t x1;
45 uint64_t x2;
46 uint64_t x3;
47 uint64_t x4;
48 uint64_t x5;
49 uint64_t x6;
50 uint64_t x7;
51 uint64_t x8;
52 uint64_t x9;
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/trusted-firmware-a/bl32/tsp/
A Dtsp_private.h67 uint64_t arg1,
68 uint64_t arg2,
69 uint64_t arg3,
70 uint64_t arg4,
71 uint64_t arg5,
72 uint64_t arg6,
73 uint64_t arg7);
75 uint64_t arg1,
133 uint64_t arg1,
134 uint64_t arg2,
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A Dtsp_main.c294 uint64_t arg1, in tsp_system_off_main()
295 uint64_t arg2, in tsp_system_off_main()
296 uint64_t arg3, in tsp_system_off_main()
297 uint64_t arg4, in tsp_system_off_main()
298 uint64_t arg5, in tsp_system_off_main()
299 uint64_t arg6, in tsp_system_off_main()
300 uint64_t arg7) in tsp_system_off_main()
326 uint64_t arg1, in tsp_system_reset_main()
327 uint64_t arg2, in tsp_system_reset_main()
328 uint64_t arg3, in tsp_system_reset_main()
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/trusted-firmware-a/plat/xilinx/zynqmp/pm_service/
A Dpm_svc_main.c261 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
262 uint64_t x4, void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
293 uint64_t address = (uint64_t)pm_arg[2] << 32; in pm_smc_handler()
365 (uint64_t)buff[1] | ((uint64_t)buff[2] << 32)); in pm_smc_handler()
404 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
416 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
439 (uint64_t)result[0] | ((uint64_t)result[1] << 32), in pm_smc_handler()
440 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); in pm_smc_handler()
491 (uint64_t)data[2] | ((uint64_t)data[3] << 32)); in pm_smc_handler()
617 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32)); in pm_smc_handler()
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A Dpm_svc_main.h13 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
14 uint64_t x4, void *cookie, void *handle,
15 uint64_t flags);
17 uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
18 uint64_t x4, void *cookie, void *handle,
19 uint64_t flags);
/trusted-firmware-a/plat/xilinx/versal/pm_service/
A Dpm_svc_main.c132 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
133 uint64_t x4, void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
219 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32), in pm_smc_handler()
220 (uint64_t)buff[1] | ((uint64_t)buff[2] << 32)); in pm_smc_handler()
247 (uint64_t)result[0] | ((uint64_t)result[1] << 32), in pm_smc_handler()
248 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); in pm_smc_handler()
264 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
278 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
292 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); in pm_smc_handler()
303 (uint64_t)data[1] | ((uint64_t)data[2] << 32)); in pm_smc_handler()
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/trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/mce/
A Dnvg.c29 uint64_t nvg_get_version(void) in nvg_get_version()
33 return (uint64_t)nvg_get_result(); in nvg_get_version()
45 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); in nvg_set_wake_time()
64 uint64_t val = 0; in nvg_update_cstate_info()
127 (uint64_t)core & MCE_CORE_ID_MASK); in nvg_online_core()
149 (uint64_t)gsc_idx); in nvg_update_ccplex_gsc()
182 uint64_t val = 0ULL; in nvg_enter_cstate()
212 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_enable_strict_checking_mode()
220 uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET | in nvg_verify_strict_checking_mode()
237 (uint64_t)TEGRA_NVG_REBOOT); in nvg_system_reboot()
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/trusted-firmware-a/plat/mediatek/common/
A Dmtk_plat_common.h42 uint64_t pc;
43 uint64_t r0;
44 uint64_t r1;
45 uint64_t r2;
46 uint64_t k32_64;
50 uint64_t bootarg_loc;
51 uint64_t bootarg_size;
52 uint64_t bl33_start_addr;
53 uint64_t tee_info_addr;
74 void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4);
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/trusted-firmware-a/lib/extensions/amu/aarch64/
A Damu.c33 uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
35 uint64_t group1_cnts[AMU_GROUP1_MAX_COUNTERS];
41 uint64_t group1_voffsets[AMU_GROUP1_MAX_COUNTERS];
138 uint64_t value = read_amcntenset0_el0(); in write_amcntenset0_el0_px()
148 uint64_t value = read_amcntenset1_el0(); in write_amcntenset1_el0_px()
158 uint64_t value = read_amcntenclr0_el0(); in write_amcntenclr0_el0_px()
168 uint64_t value = read_amcntenclr1_el0(); in write_amcntenclr1_el0_px()
199 uint64_t id_aa64pfr0_el1_amu; /* AMU version */ in amu_enable()
441 uint64_t i, j; in amu_context_save()
446 uint64_t id_aa64pfr0_el1_amu; /* AMU version */ in amu_context_save()
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/trusted-firmware-a/include/services/
A Dspm_mm_partition.h26 uint64_t mpidr;
33 uint64_t sp_mem_base;
34 uint64_t sp_mem_limit;
35 uint64_t sp_image_base;
36 uint64_t sp_stack_base;
37 uint64_t sp_heap_base;
39 uint64_t sp_shared_buf_base;
40 uint64_t sp_image_size;
41 uint64_t sp_pcpu_stack_size;
42 uint64_t sp_heap_size;
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A Drmmd_svc.h14 uint64_t rmmd_rmi_handler(uint32_t smc_fid,
15 uint64_t x1,
16 uint64_t x2,
17 uint64_t x3,
18 uint64_t x4,
21 uint64_t flags);
24 uint64_t x1,
25 uint64_t x2,
26 uint64_t x3,
27 uint64_t x4,
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/trusted-firmware-a/plat/rockchip/rk3399/drivers/dp/
A Dcdn_dp.c27 static uint64_t *hdcp_key_pdata;
32 uint64_t dp_hdcp_ctrl(uint64_t type) in dp_hdcp_ctrl()
37 hdcp_key_pdata = (uint64_t *)&key; in dp_hdcp_ctrl()
40 if (hdcp_key_pdata == (uint64_t *)(&key + 1)) in dp_hdcp_ctrl()
50 uint64_t dp_hdcp_store_key(uint64_t x1, in dp_hdcp_store_key()
51 uint64_t x2, in dp_hdcp_store_key()
52 uint64_t x3, in dp_hdcp_store_key()
53 uint64_t x4, in dp_hdcp_store_key()
54 uint64_t x5, in dp_hdcp_store_key()
55 uint64_t x6) in dp_hdcp_store_key()
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A Dcdn_dp.h40 uint64_t dp_hdcp_ctrl(uint64_t type);
42 uint64_t dp_hdcp_store_key(uint64_t x1,
43 uint64_t x2,
44 uint64_t x3,
45 uint64_t x4,
46 uint64_t x5,
47 uint64_t x6);
/trusted-firmware-a/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c22 uint64_t val = 0ULL; in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
51 uint64_t val = 0ULL; in nvg_update_cstate_info()
107 (uint64_t)type), (uint64_t)time); in nvg_update_crossover_time()
115 uint64_t ret; in nvg_read_cstate_stats()
130 (uint64_t)state)); in nvg_read_cstate_stats()
139 uint64_t val; in nvg_write_cstate_stats()
158 (uint64_t)state), val); in nvg_write_cstate_stats()
175 uint64_t val; in nvg_is_sc7_allowed()
226 ((uint64_t)core & MCE_CORE_ID_MASK)); in nvg_online_core()
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A Dmce.c116 uint64_t mpidr = read_mpidr(); in mce_get_curr_cpu_ari_base()
136 uint64_t mpidr = read_mpidr(); in mce_get_curr_cpu_ops()
158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler()
159 uint64_t arg2) in mce_command_handler()
164 uint64_t ret64 = 0, arg3, arg4, arg5; in mce_command_handler()
176 case (uint64_t)MCE_CMD_ENTER_CSTATE: in mce_command_handler()
236 case (uint64_t)MCE_CMD_ONLINE_CORE: in mce_command_handler()
241 case (uint64_t)MCE_CMD_CC3_CTRL: in mce_command_handler()
246 case (uint64_t)MCE_CMD_ECHO_DATA: in mce_command_handler()
340 case (uint64_t)MCE_CMD_MISC_CCPLEX: in mce_command_handler()
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/trusted-firmware-a/drivers/arm/gic/v3/
A Dgic600ae_fmu_helpers.c50 uint64_t status; in wait_until_fmu_is_idle()
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr()
100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr()
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U); in gic_fmu_read_errctlr()
132 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U); in gic_fmu_read_errstatus()
141 uint64_t gic_fmu_read_errgsr(uintptr_t base) in gic_fmu_read_errgsr()
147 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO); in gic_fmu_read_errgsr()
172 uint64_t gic_fmu_read_pingmask(uintptr_t base) in gic_fmu_read_pingmask()
178 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_PINGMASK_LO); in gic_fmu_read_pingmask()
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/trusted-firmware-a/lib/gpt_rme/
A Dgpt_rme_private.h40 ((uint64_t)(_gpi) << 4*1) | \
41 ((uint64_t)(_gpi) << 4*2) | \
42 ((uint64_t)(_gpi) << 4*3) | \
43 ((uint64_t)(_gpi) << 4*4) | \
44 ((uint64_t)(_gpi) << 4*5) | \
45 ((uint64_t)(_gpi) << 4*6) | \
46 ((uint64_t)(_gpi) << 4*7) | \
47 ((uint64_t)(_gpi) << 4*8) | \
48 ((uint64_t)(_gpi) << 4*9) | \
49 ((uint64_t)(_gpi) << 4*10) | \
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/trusted-firmware-a/services/std_svc/rmmd/
A Drmmd_main.c52 uint32_t dst_sec_state, uint64_t x1,
53 uint64_t x2, uint64_t x3, uint64_t x4,
62 uint64_t rc; in rmmd_rmm_sync_entry()
124 uint64_t rc; in rmm_init()
196 uint64_t x2, uint64_t x3, uint64_t x4, in rmmd_smc_forward()
218 uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, in rmmd_rmi_handler()
219 uint64_t x3, uint64_t x4, void *cookie, in rmmd_rmi_handler()
220 void *handle, uint64_t flags) in rmmd_rmi_handler()
322 uint64_t rmmd_gtsi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, in rmmd_gtsi_handler()
323 uint64_t x3, uint64_t x4, void *cookie, in rmmd_gtsi_handler()
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/trusted-firmware-a/plat/nvidia/tegra/include/
A Dtegra_private.h37 uint64_t tzdram_size;
39 uint64_t tzdram_base;
45 uint64_t boot_profiler_shmem_base;
47 uint64_t sc7entry_fw_size;
49 uint64_t sc7entry_fw_base;
128 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
145 uint64_t x1,
146 uint64_t x2,
147 uint64_t x3,
148 uint64_t x4,
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/trusted-firmware-a/tools/renesas/rcar_layout_create/
A Dsa6.c135 const uint64_t __attribute__ ((section (".sa6_image_num"))) image_num = RCAR_IMAGE_NUM;
136 const uint64_t __attribute__ ((section (".sa6_bl31src_addr"))) bl31src_addr = RCAR_BL31SRC_ADDRESS;
137 const uint64_t __attribute__ ((section (".sa6_bl31partition"))) bl31partition = RCAR_BL31_PARTITION;
138 const uint64_t __attribute__ ((section (".sa6_bl32src_addr"))) bl32src_addr = RCAR_BL32SRC_ADDRESS;
139 const uint64_t __attribute__ ((section (".sa6_bl32partition"))) bl32partition = RCAR_BL32_PARTITION;
140 const uint64_t __attribute__ ((section (".sa6_bl33src_addr"))) bl33src_addr = RCAR_BL33SRC_ADDRESS;
141 const uint64_t __attribute__ ((section (".sa6_bl33partition"))) bl33partition = RCAR_BL33_PARTITION;
142 const uint64_t __attribute__ ((section (".sa6_bl332src_addr"))) bl332src_addr = RCAR_BL332SRC_ADDRE…
143 const uint64_t __attribute__ ((section (".sa6_bl332partition")))bl332partition = RCAR_BL332_PARTITI…
144 const uint64_t __attribute__ ((section (".sa6_bl333src_addr"))) bl333src_addr = RCAR_BL333SRC_ADDRE…
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/trusted-firmware-a/tools/renesas/rzg_layout_create/
A Dsa6.c135 const uint64_t __attribute__ ((section(".sa6_image_num")))
137 const uint64_t __attribute__ ((section(".sa6_bl31src_addr")))
139 const uint64_t __attribute__ ((section(".sa6_bl31partition")))
141 const uint64_t __attribute__ ((section(".sa6_bl32src_addr")))
143 const uint64_t __attribute__ ((section(".sa6_bl32partition")))
145 const uint64_t __attribute__ ((section(".sa6_bl33src_addr")))
147 const uint64_t __attribute__ ((section(".sa6_bl33partition")))
149 const uint64_t __attribute__ ((section(".sa6_bl332src_addr")))
153 const uint64_t __attribute__ ((section(".sa6_bl333src_addr")))
157 const uint64_t __attribute__ ((section(".sa6_bl334src_addr")))
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/trusted-firmware-a/plat/mediatek/mt8173/
A Dplat_sip_calls.c31 uint64_t i; in mt_sip_set_authorized_sreg()
43 static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val) in mt_sip_pwr_on_mtcmos()
54 static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val) in mt_sip_pwr_off_mtcmos()
65 static uint64_t mt_sip_pwr_mtcmos_support(void) in mt_sip_pwr_mtcmos_support()
70 uint64_t mediatek_plat_sip_handler(uint32_t smc_fid, in mediatek_plat_sip_handler()
71 uint64_t x1, in mediatek_plat_sip_handler()
72 uint64_t x2, in mediatek_plat_sip_handler()
73 uint64_t x3, in mediatek_plat_sip_handler()
74 uint64_t x4, in mediatek_plat_sip_handler()
77 uint64_t flags) in mediatek_plat_sip_handler()
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/trusted-firmware-a/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.c13 static uint64_t dfd_base_addr;
14 static uint64_t dfd_chain_length;
15 static uint64_t dfd_cache_dump;
17 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, in dfd_setup()
18 uint64_t cache_dump) in dfd_setup()
112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher()
113 uint64_t arg2, uint64_t arg3) in dfd_smc_dispatcher()
115 uint64_t ret = 0L; in dfd_smc_dispatcher()
/trusted-firmware-a/plat/nvidia/tegra/soc/t194/drivers/include/
A Dmce_private.h47 uint64_t nvg_get_version(void);
51 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
52 uint64_t nvg_get_cstate_stat_query_value(void);
65 void nvg_set_request_data(uint64_t req, uint64_t data);
66 void nvg_set_request(uint64_t req);
67 uint64_t nvg_get_result(void);
68 uint64_t nvg_cache_clean(void);
69 uint64_t nvg_cache_clean_inval(void);
70 uint64_t nvg_cache_inval_all(void);
/trusted-firmware-a/services/std_svc/spm_mm/
A Dspm_mm_main.c90 uint64_t rc; in spm_sp_synchronous_entry()
137 uint64_t rc; in spm_init()
187 uint64_t spm_mm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3) in spm_mm_sp_call()
189 uint64_t rc; in spm_mm_sp_call()
216 static uint64_t mm_communicate(uint32_t smc_fid, uint64_t mm_cookie, in mm_communicate()
220 uint64_t rc; in mm_communicate()
273 uint64_t x1, in spm_mm_smc_handler()
274 uint64_t x2, in spm_mm_smc_handler()
275 uint64_t x3, in spm_mm_smc_handler()
276 uint64_t x4, in spm_mm_smc_handler()
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