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Searched refs:CLK_ROOT_SOURCE_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mm.c156 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
162 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
164 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
282 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
288 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
315 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
417 CLK_ROOT_SOURCE_SEL(2)); in clock_init()
439 CLK_ROOT_SOURCE_SEL(3)); in clock_init()
444 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
448 CLK_ROOT_SOURCE_SEL(1)); in clock_init()
[all …]
A Dclock_imx8mq.c376 CLK_ROOT_SOURCE_SEL(4) | in mxs_set_lcdclk()
386 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
388 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
390 CLK_ROOT_SOURCE_SEL(0)); in init_wdog_clk()
413 CLK_ROOT_SOURCE_SEL(0)); in init_uart_clk()
473 CLK_ROOT_SOURCE_SEL(7)); in set_clk_qspi()
566 CLK_ROOT_SOURCE_SEL(1)); in dram_enable_bypass()
572 CLK_ROOT_SOURCE_SEL(0)); in dram_disable_bypass()
574 CLK_ROOT_SOURCE_SEL(4) | in dram_disable_bypass()
706 CLK_ROOT_SOURCE_SEL(0)); in clock_init()
[all …]
/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c113 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | in ddr_init()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dclock.h214 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) macro

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