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Searched refs:DDR_CTRL_AUTO_REFRESH (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca953x/
A Dddr.c19 #define DDR_CTRL_AUTO_REFRESH BIT(2) macro
280 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
282 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
370 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
372 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
/u-boot/arch/mips/mach-ath79/ar933x/
A Dddr.c18 #define DDR_CTRL_AUTO_REFRESH BIT(2) macro
153 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
154 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()

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