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Searched refs:DDR_CTRL_UPD_MRS (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/ar933x/
A Dddr.c20 #define DDR_CTRL_UPD_MRS BIT(0) macro
147 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
159 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
199 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
214 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
/u-boot/arch/mips/mach-ath79/qca953x/
A Dddr.c21 #define DDR_CTRL_UPD_MRS BIT(0) macro
272 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
290 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
362 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
380 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()

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