Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 13 of 13) sorted by relevance
| /u-boot/drivers/pinctrl/renesas/ |
| A D | pfc-r8a7791.c | 5706 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5766 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5803 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5840 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5879 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5924 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5963 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
6004 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6046 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6090 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
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| A D | pfc-r8a7790.c | 4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4989 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5027 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5057 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5091 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5125 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5163 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5200 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5236 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5278 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
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| A D | pfc-r8a7794.c | 4860 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4915 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4956 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4992 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5034 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5070 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5107 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5154 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5192 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5228 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
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| A D | pfc-r8a7792.c | 2402 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2461 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2520 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2569 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2616 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2658 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2699 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2742 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
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| A D | sh_pfc.h | 157 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ macro
656 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
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| A D | pfc-r8a77995.c | 2768 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2801 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
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| A D | pfc-r8a7795.c | 5604 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5630 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5658 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
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| A D | pfc-r8a7796.c | 5517 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5543 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5571 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
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| A D | pfc-r8a77965.c | 5813 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5839 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5867 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
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| A D | pfc-r8a77990.c | 4943 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4972 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
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| A D | pfc-r8a77970.c | 2380 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
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| A D | pfc-r8a77980.c | 2802 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
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| /u-boot/include/ |
| A D | sh_pfc.h | 56 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
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