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Searched refs:PORT_SCR_CTL (Results 1 – 2 of 2) sorted by relevance

/u-boot/board/highbank/
A Dahci.c190 writel(0x301, port_mmio + PORT_SCR_CTL); in ahci_link_up()
192 writel(0x300, port_mmio + PORT_SCR_CTL); in ahci_link_up()
/u-boot/include/
A Dahci.h56 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ macro

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