Searched refs:ddr_fsp0_cfg (Results 1 – 12 of 12) sorted by relevance
| /u-boot/board/google/imx8mq_phanbell/ |
| A D | lpddr4_timing_1g.c | 992 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1699 .fsp_cfg = ddr_fsp0_cfg,
1700 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/technexion/pico-imx8mq/ |
| A D | lpddr4_timing_1gb.c | 994 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1701 .fsp_cfg = ddr_fsp0_cfg,
1702 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| A D | lpddr4_timing_2gb.c | 994 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1701 .fsp_cfg = ddr_fsp0_cfg,
1702 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| A D | lpddr4_timing_3gb.c | 994 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1701 .fsp_cfg = ddr_fsp0_cfg,
1702 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| A D | lpddr4_timing_4gb.c | 994 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1701 .fsp_cfg = ddr_fsp0_cfg,
1702 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/beacon/imx8mn/ |
| A D | lpddr4_2g_timing.c | 679 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1401 .fsp_cfg = ddr_fsp0_cfg,
1402 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| A D | lpddr4_timing.c | 676 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1394 .fsp_cfg = ddr_fsp0_cfg,
1395 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/phytec/phycore_imx8mm/ |
| A D | lpddr4_timing.c | 1048 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1807 .fsp_cfg = ddr_fsp0_cfg,
1808 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/phytec/phycore_imx8mp/ |
| A D | lpddr4_timing.c | 1053 static struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1810 .fsp_cfg = ddr_fsp0_cfg,
1811 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/freescale/imx8mn_evk/ |
| A D | ddr4_timing.c | 794 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1174 .fsp_cfg = ddr_fsp0_cfg,
1175 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/freescale/imx8mp_evk/ |
| A D | lpddr4_timing.c | 1052 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1809 .fsp_cfg = ddr_fsp0_cfg,
1810 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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| /u-boot/board/toradex/verdin-imx8mm/ |
| A D | lpddr4_timing.c | 1052 struct dram_cfg_param ddr_fsp0_cfg[] = { variable
1811 .fsp_cfg = ddr_fsp0_cfg,
1812 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
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