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/u-boot/arch/arm/mach-tegra/tegra124/
A Dpsci.c26 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in psci_board_init() local
46 writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); in psci_board_init()
47 writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); in psci_board_init()
48 writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); in psci_board_init()
50 writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); in psci_board_init()
51 writel(EVENT_MODE_STOP, &flow->halt_cpu2_events); in psci_board_init()
52 writel(EVENT_MODE_STOP, &flow->halt_cpu3_events); in psci_board_init()
54 while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) || in psci_board_init()
55 !(readl(&flow->cpu2_csr) & CSR_PWR_OFF_STS) || in psci_board_init()
56 !(readl(&flow->cpu3_csr) & CSR_PWR_OFF_STS)) in psci_board_init()
A Dcpu.c111 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in tegra124_ram_repair() local
119 clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN); in tegra124_ram_repair()
123 setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); in tegra124_ram_repair()
128 val = readl(&flow->ram_repair); in tegra124_ram_repair()
134 setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); in tegra124_ram_repair()
139 val = readl(&flow->ram_repair_cluster1); in tegra124_ram_repair()
152 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in tegra124_init_clocks() local
161 clrbits_le32(&flow->cluster_control, 1); in tegra124_init_clocks()
/u-boot/arch/arm/mach-tegra/tegra30/
A Dcpu.c90 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in t30_init_clocks() local
95 clrbits_le32(flow->cluster_control, 1 << 0); in t30_init_clocks()
132 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in set_cpu_running() local
135 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events); in set_cpu_running()
/u-boot/arch/arm/mach-tegra/tegra20/
A Dwarmboot_avp.c27 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in wb_start() local
80 writel(reg, &flow->halt_cop_events); in wb_start()
93 writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); in wb_start()
195 writel(0, flow->halt_cpu_events); in wb_start()
217 writel(reg, flow->halt_cop_events); in wb_start()
/u-boot/tools/kermit/
A Dsend_cmd7 set flow-control none
A Dsend_image9 set flow-control none
A Ddot.kermrc5 set flow-control none
A Dflash_param12 set flow-control xon/xoff
/u-boot/drivers/usb/eth/
A Dlan75xx.c64 uint32_t flow = 0, fct_flow = 0; in lan75xx_update_flowcontrol() local
67 ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); in lan75xx_update_flowcontrol()
74 return lan7x_write_reg(udev, FLOW, flow); in lan75xx_update_flowcontrol()
A Dlan78xx.c189 uint32_t flow = 0, fct_flow = 0; in lan78xx_update_flowcontrol() local
192 ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow); in lan78xx_update_flowcontrol()
199 return lan7x_write_reg(udev, FLOW, flow); in lan78xx_update_flowcontrol()
A Dlan7x.c266 uint32_t *flow, uint32_t *fct_flow) in lan7x_update_flowcontrol() argument
283 *flow = (FLOW_CR_TX_FCEN | 0xFFFF); in lan7x_update_flowcontrol()
296 *flow |= FLOW_CR_RX_FCEN; in lan7x_update_flowcontrol()
A Dlan7x.h222 uint32_t *flow, uint32_t *fct_flow);
/u-boot/doc/board/xilinx/
A Dzynqmp.rst39 U-Boot SPL flow
42 For getting U-Boot SPL flow up and running it is necessary to do some additional
90 U-Boot itself can run from EL3 to EL1. Without ATF U-Boot runs in EL3. Boot flow
92 flow is U-Boot SPL->ATF->U-Boot in EL2. As the part of build process u-boot.itb
/u-boot/doc/device-tree-bindings/serial/
A D8250.txt43 - auto-flow-control: one way to enable automatic flow control support. The
/u-boot/arch/arm/mach-tegra/tegra114/
A Dcpu.c114 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; in t114_init_clocks() local
120 clrbits_le32(&flow->cluster_control, 1); in t114_init_clocks()
/u-boot/doc/
A DREADME.vxworks29 DTB for some boards. With that, the exact same bootm flow as used by Linux is
32 DTB will be used. Otherwise it falls back to the legacy bootm flow.
34 For legacy bootm flow, make sure the least significant bit of flags in bootargs
A DREADME.SPL99 will give stack usage information and cflow can construct program flow.
113 not usually important to understanding the flow, however.
/u-boot/doc/android/
A Dbcb.rst28 * Android-specific bootloader flow [3]_
99 ("[U-Boot,5/6] Initial support for the Android Bootloader flow")
/u-boot/doc/board/google/
A Dchromebook_coral.rst19 Boot flow - TPL
62 Boot flow - SPL
94 Boot flow - U-Boot pre-relocation
114 Boot flow - U-Boot post-relocation
237 Also see [2] for information about the boot flow used by coreboot. It is
/u-boot/doc/uImage.FIT/
A Dmulti_spl.its11 * same flow as booting U-Boot. Changing image type will result skipping
/u-boot/arch/arm/
A DKconfig.debug61 bool "Enable flow control for 8250 UART"
/u-boot/board/ti/j721e/
A DREADME25 Boot flow is similar to that of AM65x SoC and extending it with remoteproc
26 support. Below is the pictorial representation of boot flow:
/u-boot/board/freescale/ls1012afrdm/
A DREADME31 - UART (Console): UART1 (Without flow control) for console
/u-boot/doc/board/microchip/
A Dmpfs_icicle.rst49 boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded)
50 as HSS payload (Custom boot-flow)
52 Microchip boot-flow
57 Build the HSS (Hart Software Services) - Microchip boot-flow argument
68 Alternatively, copy the default config for Microchip boot-flow.
87 Creating the HSS payload - Microchip boot-flow argument
116 Custom boot-flow
141 Build the HSS (Hart Software Services)- Custom boot-flow argument
152 Alternatively, copy the default custom config for Custom boot-flow.
164 Creating the HSS payload - Custom boot-flow argument
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/u-boot/board/ti/am65x/
A DREADME22 the following reasons the boot flow is designed as mentioned:
29 3. In production boot flow, we might not like to use full u-boot,
30 instead use Flacon boot flow to reduce boot time.

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