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/u-boot/arch/arm/dts/
A Dexynos5250-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
45 interrupt-controller;
53 interrupt-controller;
61 interrupt-controller;
69 interrupt-controller;
77 interrupt-controller;
[all …]
A Dexynos4x12-pinctrl.dtsi21 interrupt-controller;
22 #interrupt-cells = <2>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
37 interrupt-controller;
45 interrupt-controller;
53 interrupt-controller;
61 interrupt-controller;
69 interrupt-controller;
77 interrupt-controller;
[all …]
A Dexynos4210-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
39 interrupt-controller;
47 interrupt-controller;
55 interrupt-controller;
63 interrupt-controller;
71 interrupt-controller;
79 interrupt-controller;
87 interrupt-controller;
[all …]
A Dexynos54xx-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
31 interrupt-controller;
33 #interrupt-cells = <2>;
42 interrupt-controller;
53 interrupt-controller;
61 interrupt-controller;
72 interrupt-controller;
80 interrupt-controller;
88 interrupt-controller;
[all …]
A Dexynos4.dtsi25 #interrupt-cells = <2>;
26 interrupt-controller;
32 #interrupt-cells = <3>;
33 interrupt-controller;
73 interrupt-parent = <&gic>;
82 interrupt-parent = <&gic>;
91 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
109 interrupt-parent = <&gic>;
118 interrupt-parent = <&gic>;
[all …]
A Darmada-xp-mv78460.dtsi122 #interrupt-cells = <1>;
140 #interrupt-cells = <1>;
158 #interrupt-cells = <1>;
176 #interrupt-cells = <1>;
194 #interrupt-cells = <1>;
212 #interrupt-cells = <1>;
230 #interrupt-cells = <1>;
248 #interrupt-cells = <1>;
307 interrupt-controller;
322 interrupt-controller;
[all …]
A Darmada-xp-mv78260.dtsi101 #interrupt-cells = <1>;
119 #interrupt-cells = <1>;
137 #interrupt-cells = <1>;
155 #interrupt-cells = <1>;
173 #interrupt-cells = <1>;
191 #interrupt-cells = <1>;
209 #interrupt-cells = <1>;
227 #interrupt-cells = <1>;
268 interrupt-controller;
283 interrupt-controller;
[all …]
A Dmt8518.dtsi10 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&sysirq>;
27 gic: interrupt-controller@0c000000 {
29 #interrupt-cells = <3>;
30 interrupt-parent = <&gic>;
31 interrupt-controller;
38 sysirq: interrupt-controller@10200a80 {
40 interrupt-controller;
41 #interrupt-cells = <3>;
42 interrupt-parent = <&gic>;
[all …]
A Dkeystone-k2e.dtsi16 interrupt-parent = <&gic>;
103 #interrupt-cells = <1>;
104 interrupt-map-mask = <0 0 0 7>;
110 pcie_msi_intc1: msi-interrupt-controller {
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 interrupt-parent = <&gic>;
124 pcie_intc1: legacy-interrupt-controller {
125 interrupt-controller;
126 #interrupt-cells = <1>;
[all …]
A Dstm32f7-pinctrl.dtsi23 interrupt-controller;
24 #interrupt-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
43 interrupt-controller;
53 interrupt-controller;
63 interrupt-controller;
73 interrupt-controller;
83 interrupt-controller;
93 interrupt-controller;
[all …]
A Darmada-xp-mv78230.dtsi86 #interrupt-cells = <1>;
90 interrupt-map-mask = <0 0 0 0>;
104 #interrupt-cells = <1>;
108 interrupt-map-mask = <0 0 0 0>;
122 #interrupt-cells = <1>;
140 #interrupt-cells = <1>;
158 #interrupt-cells = <1>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
196 interrupt-controller;
[all …]
A Dbcm2836.dtsi15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
23 interrupt-parent = <&local_intc>;
29 interrupt-parent = <&local_intc>;
72 /* Make the BCM2835-style global interrupt controller be a child of the
73 * CPU-local interrupt controller.
78 interrupt-parent = <&local_intc>;
A Dmt8516.dtsi9 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&sysirq>;
76 gic: interrupt-controller@10310000 {
78 interrupt-controller;
79 #interrupt-cells = <3>;
80 interrupt-parent = <&gic>;
89 sysirq: interrupt-controller@10200620 {
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 interrupt-parent = <&gic>;
[all …]
A Darmv7-m.dtsi3 nvic: interrupt-controller@e000e100 {
5 interrupt-controller;
6 #interrupt-cells = <1>;
20 interrupt-parent = <&nvic>;
A Dexynos4x12.dtsi46 interrupt-parent = <&mct_map>;
52 #interrupt-cells = <1>;
55 interrupt-map = <0 &gic 0 57 0>,
66 interrupt-parent = <&gic>;
73 interrupt-parent = <&gic>;
76 wakup_eint: wakeup-interrupt-controller {
78 interrupt-parent = <&gic>;
86 interrupt-parent = <&combiner>;
93 interrupt-parent = <&gic>;
100 interrupt-parent = <&gic>;
/u-boot/arch/mips/dts/
A Dimg,boston.dts34 gic: interrupt-controller {
37 interrupt-controller;
38 #interrupt-cells = <3>;
55 #interrupt-cells = <1>;
70 interrupt-controller;
72 #interrupt-cells = <1>;
84 #interrupt-cells = <1>;
99 interrupt-controller;
101 #interrupt-cells = <1>;
112 #interrupt-cells = <1>;
[all …]
A Djz4780.dtsi10 cpuintc: interrupt-controller {
12 #interrupt-cells = <1>;
13 interrupt-controller;
21 interrupt-controller;
22 #interrupt-cells = <1>;
24 interrupt-parent = <&cpuintc>;
74 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
116 interrupt-parent = <&intc>;
[all …]
/u-boot/doc/device-tree-bindings/interrupt-controller/
A Dinterrupts.txt11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
26 to reference multiple interrupt parents or a different interrupt parent than
39 A device is marked as an interrupt controller with the "interrupt-controller"
56 interrupt-controller;
57 #interrupt-cells = <1>;
63 interrupt-controller;
64 #interrupt-cells = <1>;
94 interrupt-controller;
121 interrupt-controller;
[all …]
A Dintel,acpi-gpe.txt3 This describes an interrupt controller which provides access to GPEs supported
9 - interrupt-controller : Identifies the node as an interrupt controller
10 - #interrupt-cells : The number of cells to define the interrupts. Must be 2:
11 cell 0: interrupt number (normally >=32 since GPEs below that are reserved)
20 interrupt-controller;
21 #interrupt-cells = <2>;
/u-boot/arch/riscv/dts/
A Dae350_32.dts39 #interrupt-cells = <1>;
40 interrupt-controller;
60 #interrupt-cells = <1>;
61 interrupt-controller;
81 #interrupt-cells = <1>;
82 interrupt-controller;
103 interrupt-controller;
135 #interrupt-cells = <1>;
136 interrupt-controller;
148 #interrupt-cells = <1>;
[all …]
A Dae350_64.dts39 #interrupt-cells = <1>;
40 interrupt-controller;
60 #interrupt-cells = <1>;
61 interrupt-controller;
81 #interrupt-cells = <1>;
82 interrupt-controller;
103 interrupt-controller;
135 #interrupt-cells = <2>;
136 interrupt-controller;
148 #interrupt-cells = <2>;
[all …]
A Dfu540-c000.dtsi35 #interrupt-cells = <1>;
37 interrupt-controller;
59 #interrupt-cells = <1>;
61 interrupt-controller;
83 #interrupt-cells = <1>;
85 interrupt-controller;
109 interrupt-controller;
133 interrupt-controller;
143 #interrupt-cells = <1>;
147 interrupt-controller;
[all …]
A Dmicrochip-mpfs-icicle-kit.dts46 #interrupt-cells = <1>;
48 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-controller;
108 #interrupt-cells = <1>;
110 interrupt-controller;
139 #interrupt-cells = <1>;
141 interrupt-controller;
172 interrupt-controller;
215 #interrupt-cells = <1>;
[all …]
/u-boot/arch/powerpc/dts/
A Dsocrates.dts68 interrupt-parent = <&mpic>;
74 interrupt-parent = <&mpic>;
83 interrupt-parent = <&mpic>;
94 interrupt-parent = <&mpic>;
126 interrupt-parent = <&mpic>;
223 interrupt-controller;
225 #interrupt-cells = <2>;
293 interrupt-controller;
297 #interrupt-cells = <3>;
328 #interrupt-cells = <1>;
[all …]
/u-boot/doc/device-tree-bindings/pci/
A Dmediatek-pcie.txt28 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
44 - #interrupt-cells: Must be 1
45 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
71 #interrupt-cells = <1>;
72 interrupt-map-mask = <0xf800 0 0 0>;
97 #interrupt-cells = <1>;
98 interrupt-map-mask = <0 0 0 0>;
107 #interrupt-cells = <1>;
108 interrupt-map-mask = <0 0 0 0>;
117 #interrupt-cells = <1>;
[all …]

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