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Searched refs:port2 (Results 1 – 25 of 26) sorted by relevance

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/u-boot/arch/mips/dts/
A Docelot_pcb123.dts66 port2: port@2 { label
A Dserval_pcb105.dts89 port2: port@2 { label
A Dserval_pcb106.dts89 port2: port@2 { label
A Dserval2_pcb112.dts93 port2: port@2 { label
A Djr2_pcb110.dts119 port2: port@2 { label
A Dluton_pcb091.dts115 port2: port@2 { label
A Docelot_pcb120.dts136 port2: port@2 { label
A Dmscc,luton.dtsi128 reg-names = "port0", "port1", "port2", "port3",
A Dluton_pcb090.dts151 port2: port@2 { label
A Dmscc,serval.dtsi168 reg-names = "port0", "port1", "port2", "port3",
A Dmscc,ocelot.dtsi138 reg-names = "port0", "port1", "port2", "port3", "port4",
A Dmscc,jr2.dtsi247 reg-names = "port0", "port1", "port2", "port3", "port4",
A Djr2_pcb111.dts243 port2: port@2 { label
/u-boot/include/
A Dfsl_usb.h39 struct ccsr_usb_port_ctrl port2; member
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dcpu_init.c96 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); in fsl_erratum_a006261_workaround()
102 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); in fsl_erratum_a006261_workaround()
947 setbits_be32(&usb_phy->port2.ctrl, in cpu_init_r()
949 setbits_be32(&usb_phy->port2.drvvbuscfg, in cpu_init_r()
951 setbits_be32(&usb_phy->port2.pwrfltcfg, in cpu_init_r()
/u-boot/doc/device-tree-bindings/phy/
A Dphy-mtk-tphy.txt116 u2 port2 0x1800 U2PHY_COM
139 u2 port2 0x2000 MISC
/u-boot/arch/arm/dts/
A Dca-presidio-engboard.dts121 * port2: phy address 3 - GMAC2: port 2
A Domap3-evm-common.dtsi169 port2-mode = "ehci-phy";
A Dsun7i-a20-lamobo-r1.dts157 port2: port@2 { label
A Dlogicpd-som-lv.dtsi147 port2-mode = "ehci-phy";
A Domap3-beagle-xm.dts348 port2-mode = "ehci-phy";
A Domap3-beagle.dts300 port2-mode = "ehci-phy";
A Dmt7623.dtsi260 reg-names = "subsys", "port0", "port1", "port2";
A Domap5-board-common.dtsi692 port2-mode = "ehci-hsic";
/u-boot/doc/device-tree-bindings/pci/
A Dmediatek-pcie.txt68 reg-names = "subsys", "port0", "port1", "port2";

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