Searched refs:receive (Results 1 – 25 of 48) sorted by relevance
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| /u-boot/include/ |
| A D | dma-uclass.h | 100 int (*receive)(struct dma *dma, void **dst, void *metadata); member
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| /u-boot/doc/device-tree-bindings/misc/misc/ |
| A D | gdsys,io-endpoint.txt | 4 that allows interconnected gdsys devices to send and receive data over the
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| /u-boot/doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ |
| A D | ucc.txt | 7 - rx-clock-name: the UCC receive clock source
20 - rx-clock : represents the UCC receive clock source.
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| /u-boot/doc/device-tree-bindings/mailbox/ |
| A D | k3-secure-proxy.txt | 6 has different address space that can be used to send or receive messages.
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| /u-boot/drivers/dma/ |
| A D | dma-uclass.c | 176 if (!ops->receive) in dma_receive()
179 return ops->receive(dma, dst, metadata); in dma_receive()
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| A D | sandbox-dma-test.c | 238 .receive = sandbox_dma_receive,
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| /u-boot/doc/device-tree-bindings/serial/ |
| A D | omap_serial.txt | 21 - dma-names : "rx" for receive channel, "tx" for transmit channel.
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| /u-boot/doc/device-tree-bindings/net/ |
| A D | ethernet.txt | 53 - rx-fifo-depth: the size of the controller's receive fifo in bytes. This
54 is used for components that can have configurable receive fifo sizes,
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| A D | snps,dwc-qos-ethernet.txt | 30 The EQOS receive path clock. The HW signal name is clk_rx_i.
34 In cases where the PHY clock is directly fed into the EQOS receive path
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| A D | altera_tse.txt | 20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
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| /u-boot/doc/device-tree-bindings/firmware/ |
| A D | ti,sci.txt | 29 "rx" - Mailbox corresponding to receive path
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| /u-boot/arch/arm/dts/ |
| A D | imx6q-hummingboard-som-v15.dts | 59 fsl,receive-eq-mdB = <3000>;
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| A D | imx6q-hummingboard.dts | 59 fsl,receive-eq-mdB = <3000>;
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| A D | imx6q-hummingboard-emmc-som-v15.dts | 60 fsl,receive-eq-mdB = <3000>;
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| A D | imx6q-tbs2910.dts | 178 fsl,receive-eq-mdB = <3000>;
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| /u-boot/doc/ |
| A D | README.440-DDR-performance | 4 these setup routines will automatically receive this performance
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| A D | README.tee | 41 driver. The main job for the driver is to receive requests from the
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| A D | README.mpc85xx | 6 be able to receive control after a single step or breakpoint:
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| /u-boot/doc/device-tree-bindings/reset/ |
| A D | reset.txt | 8 Hardware blocks typically receive a reset signal. This signal is generated by
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| /u-boot/doc/device-tree-bindings/spi/ |
| A D | spi-bus.txt | 67 Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
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| /u-boot/lib/efi_selftest/ |
| A D | efi_selftest_snp.c | 367 ret = net->receive(net, NULL, &buffer_size, &buffer, in execute()
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| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | intel,x86-broadwell-pinctrl.txt | 42 But missing pins will receive the default configuration.
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| /u-boot/Licenses/ |
| A D | gpl-2.0.txt | 24 this service if you wish), that you receive source code or can get it
35 you have. You must make sure that they, too, receive or can get the
80 source code as you receive it, in any medium, provided that you
206 all those who receive copies directly or indirectly through you, then
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| /u-boot/doc/board/intel/ |
| A D | edison.rst | 122 *** Ready to receive application ***
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| /u-boot/doc/imx/habv4/guides/ |
| A D | mx6_mx7_spl_secure_boot.txt | 150 receive a CSF binary, which contains the CSF commands, SRK table, signatures
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