| /u-boot/lib/efi_selftest/ |
| A D | efi_selftest.c | 213 unsigned int steps, unsigned int *failures) in efi_st_do_tests() argument 226 if (steps & EFI_ST_SETUP) in efi_st_do_tests() 228 if (steps & EFI_ST_EXECUTE && setup_status[i] == EFI_ST_SUCCESS) in efi_st_do_tests() 230 if (steps & EFI_ST_TEARDOWN) in efi_st_do_tests()
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| /u-boot/drivers/mtd/nand/raw/ |
| A D | mxc_nand.c | 400 for (i = 0; i < chip->ecc.steps; i++) { 426 for (i = 0; i < chip->ecc.steps; i++) { 448 int steps, size; local 454 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { 492 int eccsteps = chip->ecc.steps; 536 eccsteps = chip->ecc.steps; 555 int i, len, status, steps = chip->ecc.steps; local 559 for (i = 0; i < steps; i++) { 585 int steps, size; local 588 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { [all …]
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| A D | nand_base.c | 1804 int steps, size, ret; in nand_read_page_raw_syndrome() local 1806 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome() 1861 int eccsteps = chip->ecc.steps; in nand_read_page_swecc() 1876 eccsteps = chip->ecc.steps; in nand_read_page_swecc() 2045 eccsteps = chip->ecc.steps; in nand_read_page_hwecc() 2582 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; in nand_write_oob_syndrome() local 2592 steps = 0; in nand_write_oob_syndrome() 2600 for (i = 0; i < steps; i++) { in nand_write_oob_syndrome() 2834 int steps, size, ret; in nand_write_page_raw_syndrome() local 2836 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_write_page_raw_syndrome() [all …]
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| A D | zynq_nand.c | 592 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { in zynq_nand_write_page_hwecc() 644 int eccsteps = chip->ecc.steps; in zynq_nand_write_page_swecc() 685 for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) { in zynq_nand_read_page_hwecc() 722 eccsteps = chip->ecc.steps; in zynq_nand_read_page_hwecc() 749 int eccsteps = chip->ecc.steps; in zynq_nand_read_page_swecc() 763 eccsteps = chip->ecc.steps; in zynq_nand_read_page_swecc()
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| A D | octeontx_nand.c | 466 layout->eccbytes = nand->ecc.steps * nand->ecc.bytes; in octeontx_nand_calc_ecc_layout() 1609 int eccsteps = chip->ecc.steps; in octeontx_nand_hw_bch_read_page() 1655 int eccsteps = chip->ecc.steps; in octeontx_nand_hw_bch_write_page() 1863 __func__, ecc->steps, ecc->size, ecc->bytes); in octeontx_nfc_chip_sizing() 1868 int nsteps = ecc->steps ? ecc->steps : 1; in octeontx_nfc_chip_sizing() 1875 ecc->steps = nsteps; in octeontx_nfc_chip_sizing() 1887 if (!mtd->subpage_sft && !(ecc->steps & (ecc->steps - 1))) in octeontx_nfc_chip_sizing() 1888 mtd->subpage_sft = fls(ecc->steps) - 1; in octeontx_nfc_chip_sizing()
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| A D | lpc32xx_nand_slc.c | 433 lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps); in lpc32xx_read_page_hwecc() 470 lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps); in lpc32xx_write_page_hwecc()
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| A D | denali.c | 294 int ecc_steps = chip->ecc.steps; in denali_check_erased_page() 344 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); in denali_hw_ecc_fixup() 619 int ecc_steps = chip->ecc.steps; in denali_oob_xfer() 676 int ecc_steps = chip->ecc.steps; in denali_read_page_raw() 807 int ecc_steps = chip->ecc.steps; in denali_write_page_raw()
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| /u-boot/ |
| A D | .azure-pipelines.yml | 17 steps: 42 steps: 59 steps: 69 steps: 83 steps: 95 steps: 105 steps: 116 steps: 127 steps: 135 steps: [all …]
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| /u-boot/doc/ |
| A D | README.mxc_ocotp | 37 the steps in 46.2.1.2. 40 Program operations are implemented as explained by the steps in 46.2.1.3.
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| A D | README.pblimage | 11 Building PBL Boot Image and boot steps 32 Following steps describe it in detail.
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| A D | README.kconfig | 61 Migration steps to Kconfig 109 When adding a new board, the following steps are generally needed: 129 When removing an obsolete board, the following steps are generally needed:
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| A D | README.ublimage | 79 compile steps: 96 This steps are done automagically if you do a "make all"
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| /u-boot/tools/ |
| A D | sunxi-spl-image-builder.c | 117 int steps = info->usable_page_size / info->ecc_step_size; in write_page() local 159 offs = steps * (info->ecc_step_size + eccbytes + 4); in write_page() 168 offs = info->page_size + (steps * (eccbytes + 4)); in write_page() 177 for (i = 0; i < steps; i++) { in write_page()
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| /u-boot/arch/arm/dts/ |
| A D | sun50i-a64-pinephone-1.1.dts | 28 num-interpolated-steps = <50>;
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| A D | sun50i-a64-pinephone-1.2.dts | 29 num-interpolated-steps = <50>;
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| /u-boot/doc/driver-model/ |
| A D | serial-howto.rst | 12 The deadline for this work was the end of January 2016. If no one steps 38 this involves these steps:
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| A D | i2c-howto.rst | 22 The deadline for this work is the end of June 2017. If no one steps 48 this involves these steps:
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| /u-boot/doc/board/AndesTech/ |
| A D | adp-ag101p.rst | 29 Build and boot steps
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| /u-boot/board/boundary/nitrogen6x/ |
| A D | 6x_upgrade.txt | 21 # two steps to prevent bricking
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| /u-boot/doc/SPI/ |
| A D | README.sh_qspi_test | 2 Simple steps used to test the SH-QSPI at U-Boot
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| A D | README.ti_qspi_dra_test | 2 Simple steps used to test the QSPI at U-Boot
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| /u-boot/doc/board/emulation/ |
| A D | qemu_capsule_update.rst | 102 and used by the steps highlighted below:: 135 For embedding the public key certificate, the following steps need to 173 Build U-Boot with the following steps(QEMU ARM64):: 182 Boot the platform and perform the following steps on the U-Boot
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| /u-boot/arch/x86/dts/ |
| A D | chromebook_coral.dts | 807 * [14:8] steps of delay for HS400, each 125ps 808 * [6:0] steps of delay for SDR104/HS200, each 125ps 813 * [30:24] steps of delay for SDR50, each 125ps 814 * [22:16] steps of delay for DDR50, each 125ps 815 * [14:8] steps of delay for SDR25/HS50, each 125ps 816 * [6:0] steps of delay for SDR12, each 125ps 822 * [30:24] steps of delay for SDR50, each 125ps 823 * [22:16] steps of delay for DDR50, each 125ps 824 * [14:8] steps of delay for SDR25/HS50, each 125ps 825 * [6:0] steps of delay for SDR12, each 125ps [all …]
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| /u-boot/board/sbc8548/ |
| A D | README | 112 The following steps list how to update with the current address: 122 The "md" steps in the above are just a precautionary step that allow 131 (as a backup, etc) then the steps will become: 143 enabled) the steps will become:
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| /u-boot/doc/board/intel/ |
| A D | crownbay.rst | 9 steps as documented in the BIOS Writer Guide, including initialization of the
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