Searched refs:timing_cfg_4 (Results 1 – 16 of 16) sorted by relevance
| /u-boot/board/freescale/corenet_ds/ |
| A D | p4080ds_ddr.c | 101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /u-boot/board/kontron/sl28/ |
| A D | ddr.c | 47 .timing_cfg_4 = 0x00000001,
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| /u-boot/board/freescale/p1010rdb/ |
| A D | ddr.c | 40 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
67 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /u-boot/board/freescale/ls1043ardb/ |
| A D | ddr.h | 87 .timing_cfg_4 = 0x00000002,
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| /u-boot/drivers/ddr/fsl/ |
| A D | arm_ddr_gen3.c | 109 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen3.c | 141 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
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| A D | fsl_ddr_gen4.c | 171 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
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| A D | ctrl_regs.c | 1939 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1947 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
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| A D | interactive.c | 662 CFG_REGS(timing_cfg_4), in print_fsl_memctl_config_regs()
753 CFG_REGS(timing_cfg_4), in fsl_ddr_regs_edit()
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| /u-boot/board/Arcturus/ucp1020/ |
| A D | ddr.c | 105 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /u-boot/board/freescale/ls1021aiot/ |
| A D | ls1021aiot.c | 65 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
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| /u-boot/board/freescale/ls1021atsn/ |
| A D | ls1021atsn.c | 43 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| A D | ddr.c | 234 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /u-boot/include/ |
| A D | fsl_immap.h | 50 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ member
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| A D | fsl_ddr_sdram.h | 277 unsigned int timing_cfg_4; member
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| /u-boot/board/freescale/ls1021atwr/ |
| A D | ls1021atwr.c | 159 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
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