Searched refs:timing_cfg_6 (Results 1 – 6 of 6) sorted by relevance

/u-boot/board/freescale/ls1043ardb/
A D	ddr.h	89 .timing_cfg_6 = 0,
/u-boot/include/
A D	fsl_immap.h	52 u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */ member
A D	fsl_ddr_sdram.h	279 unsigned int timing_cfg_6; member
/u-boot/drivers/ddr/fsl/
A D	fsl_ddr_gen4.c	173 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); in fsl_ddr_set_memctl_regs()
A D	ctrl_regs.c	1987 ddr->timing_cfg_6 = (0 in set_timing_cfg_6() 1994 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
A D	interactive.c	665 CFG_REGS(timing_cfg_6), in print_fsl_memctl_config_regs() 756 CFG_REGS(timing_cfg_6), in fsl_ddr_regs_edit()

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