Searched refs:w0 (Results 1 – 13 of 13) sorted by relevance

/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A D	lowlevel.S	104 lsr w0, w0, #16 106 cmp w0, w1 231 str w0, [x1] 243 lsr w0, w0, #16 245 cmp w0, w1 266 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ 267 str w0, [x1] 273 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ 274 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ 275 str w0, [x1] [all …]
A D	ls1043a_psci.S	16 ldr w0, =0x00010000 /* PSCI v1.0 */
/u-boot/arch/arm/cpu/armv8/
A D	fel_utils.S	36 str w0, [x2] 45 str w0, [x2], #0x4 48 str w0, [x2], #0x4 51 str w0, [x2, #0x8] 54 str w0, [x2]
A D	lowlevel_init.S	16 ldr w0, =CONFIG_SPL_STACK 18 ldr w0, =CONFIG_SYS_INIT_SP_ADDR
A D	psci.S	16 mov w0, #ARM_PSCI_RET_NI; \ 165 cmp w10, w0 177 cmp w0, w9 180 cmp w0, w9
/u-boot/arch/arm/cpu/armv8/bcmns3/
A D	lowlevel.S	17 mov w0, #600 19 mul w0, w0, w6
/u-boot/arch/arm/lib/
A D	gic_64.S	56 mov w0, #3 /* EnableGrp0 | EnableGrp1 */ 57 str w0, [x1] 59 mov w0, #1 << 7 /* allow NS access to GICC_PMR */ 60 str w0, [x1, #4] /* GICC_PMR */
A D	relocate_64.S	87 0: tbz w0, #2, 5f /* skip flushing cache if disabled */ 88 tbz w0, #12, 4f /* skip invalidating i-cache if disabled */
/u-boot/arch/nios2/lib/
A D	longlong.h	113 #define umul_ppmm(w1, w0, u, v) \ argument 117 smul_ppmm (__w1, w0, __xm0, __xm1); \ 125 #define umul_ppmm(w1, w0, u, v) \ argument 146 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
/u-boot/arch/m68k/lib/
A D	muldi3.c	15 #define umul_ppmm(w1, w0, u, v) \ argument 36 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
/u-boot/arch/microblaze/lib/
A D	muldi3.c	17 #define umul_ppmm(w1, w0, u, v) \ argument 38 (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
/u-boot/include/zfs/
A D	spa.h	244 #define ZIO_SET_CHECKSUM(zcp, w0, w1, w2, w3) \ argument 246 (zcp)->zc_word[0] = w0; \
/u-boot/doc/develop/
A D	crash_dumps.rst	120 10200: 52800020 mov w0, #0x1 // #1

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Last Index update Sat Jun 03 09:59:21 CST 2023