1NXP i.MX System Controller Firmware (SCFW) 2-------------------------------------------------------------------- 3 4The System Controller Firmware (SCFW) is a low-level system function 5which runs on a dedicated Cortex-M core to provide power, clock, and 6resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 7(QM, QP), and i.MX8QX (QXP, DX). 8 9The AP communicates with the SC using a multi-ported MU module found 10in the LSIO subsystem. The current definition of this MU module provides 115 remote AP connections to the SC to support up to 5 execution environments 12(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 13with the LSIO DSC IP bus. The SC firmware will communicate with this MU 14using the MSI bus. 15 16System Controller Device Node: 17============================================================ 18 19The scu node with the following properties shall be under the /firmware/ node. 20 21Required properties: 22------------------- 23- compatible: should be "fsl,imx-scu". 24- mbox-names: should include "tx0", "tx1", "tx2", "tx3", 25 "rx0", "rx1", "rx2", "rx3"; 26 include "gip3" if want to support general MU interrupt. 27- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 28 rx, and 1 optional MU channel for general interrupt. 29 All MU channels must be in the same MU instance. 30 Cross instances are not allowed. The MU instance can only 31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need 32 to make sure use the one which is not conflict with other 33 execution environments. e.g. ATF. 34 Note: 35 Channel 0 must be "tx0" or "rx0". 36 Channel 1 must be "tx1" or "rx1". 37 Channel 2 must be "tx2" or "rx2". 38 Channel 3 must be "tx3" or "rx3". 39 General interrupt rx channel must be "gip3". 40 e.g. 41 mboxes = <&lsio_mu1 0 0 42 &lsio_mu1 0 1 43 &lsio_mu1 0 2 44 &lsio_mu1 0 3 45 &lsio_mu1 1 0 46 &lsio_mu1 1 1 47 &lsio_mu1 1 2 48 &lsio_mu1 1 3 49 &lsio_mu1 3 3>; 50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 51 for detailed mailbox binding. 52 53Note: Each mu which supports general interrupt should have an alias correctly 54numbered in "aliases" node. 55e.g. 56aliases { 57 mu1 = &lsio_mu1; 58}; 59 60i.MX SCU Client Device Node: 61============================================================ 62 63Client nodes are maintained as children of the relevant IMX-SCU device node. 64 65Power domain bindings based on SCU Message Protocol 66------------------------------------------------------------ 67 68This binding for the SCU power domain providers uses the generic power 69domain binding[2]. 70 71Required properties: 72- compatible: Should be one of: 73 "fsl,imx8qm-scu-pd", 74 "fsl,imx8qxp-scu-pd" 75 followed by "fsl,scu-pd" 76 77- #power-domain-cells: Must be 1. Contains the Resource ID used by 78 SCU commands. 79 See detailed Resource ID list from: 80 include/dt-bindings/firmware/imx/rsrc.h 81 82Clock bindings based on SCU Message Protocol 83------------------------------------------------------------ 84 85This binding uses the common clock binding[1]. 86 87Required properties: 88- compatible: Should be one of: 89 "fsl,imx8qm-clk" 90 "fsl,imx8qxp-clk" 91 followed by "fsl,scu-clk" 92- #clock-cells: Should be 2. 93 Contains the Resource and Clock ID value. 94- clocks: List of clock specifiers, must contain an entry for 95 each required entry in clock-names 96- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" 97 98The clock consumer should specify the desired clock by having the clock 99ID in its "clocks" phandle cell. 100 101See the full list of clock IDs from: 102include/dt-bindings/clock/imx8qxp-clock.h 103 104Pinctrl bindings based on SCU Message Protocol 105------------------------------------------------------------ 106 107This binding uses the i.MX common pinctrl binding[3]. 108 109Required properties: 110- compatible: Should be one of: 111 "fsl,imx8qm-iomuxc", 112 "fsl,imx8qxp-iomuxc", 113 "fsl,imx8dxl-iomuxc". 114 115Required properties for Pinctrl sub nodes: 116- fsl,pins: Each entry consists of 3 integers which represents 117 the mux and config setting for one pin. The first 2 118 integers <pin_id mux_mode> are specified using a 119 PIN_FUNC_ID macro, which can be found in 120 <dt-bindings/pinctrl/pads-imx8qm.h>, 121 <dt-bindings/pinctrl/pads-imx8qxp.h>, 122 <dt-bindings/pinctrl/pads-imx8dxl.h>. 123 The last integer CONFIG is the pad setting value like 124 pull-up on this pin. 125 126 Please refer to i.MX8QXP Reference Manual for detailed 127 CONFIG settings. 128 129[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 130[2] Documentation/devicetree/bindings/power/power-domain.yaml 131[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 132 133RTC bindings based on SCU Message Protocol 134------------------------------------------------------------ 135 136Required properties: 137- compatible: should be "fsl,imx8qxp-sc-rtc"; 138 139OCOTP bindings based on SCU Message Protocol 140------------------------------------------------------------ 141Required properties: 142- compatible: Should be one of: 143 "fsl,imx8qm-scu-ocotp", 144 "fsl,imx8qxp-scu-ocotp". 145- #address-cells: Must be 1. Contains byte index 146- #size-cells: Must be 1. Contains byte length 147 148Optional Child nodes: 149 150- Data cells of ocotp: 151 Detailed bindings are described in bindings/nvmem/nvmem.txt 152 153Watchdog bindings based on SCU Message Protocol 154------------------------------------------------------------ 155 156Required properties: 157- compatible: should be: 158 "fsl,imx8qxp-sc-wdt" 159 followed by "fsl,imx-sc-wdt"; 160Optional properties: 161- timeout-sec: contains the watchdog timeout in seconds. 162 163SCU key bindings based on SCU Message Protocol 164------------------------------------------------------------ 165 166Required properties: 167- compatible: should be: 168 "fsl,imx8qxp-sc-key" 169 followed by "fsl,imx-sc-key"; 170- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml 171 172Thermal bindings based on SCU Message Protocol 173------------------------------------------------------------ 174 175Required properties: 176- compatible: Should be : 177 "fsl,imx8qxp-sc-thermal" 178 followed by "fsl,imx-sc-thermal"; 179 180- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml 181 for a description. 182 183Example (imx8qxp): 184------------- 185aliases { 186 mu1 = &lsio_mu1; 187}; 188 189lsio_mu1: mailbox@5d1c0000 { 190 ... 191 #mbox-cells = <2>; 192}; 193 194firmware { 195 scu { 196 compatible = "fsl,imx-scu"; 197 mbox-names = "tx0", "tx1", "tx2", "tx3", 198 "rx0", "rx1", "rx2", "rx3", 199 "gip3"; 200 mboxes = <&lsio_mu1 0 0 201 &lsio_mu1 0 1 202 &lsio_mu1 0 2 203 &lsio_mu1 0 3 204 &lsio_mu1 1 0 205 &lsio_mu1 1 1 206 &lsio_mu1 1 2 207 &lsio_mu1 1 3 208 &lsio_mu1 3 3>; 209 210 clk: clk { 211 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 212 #clock-cells = <2>; 213 }; 214 215 iomuxc { 216 compatible = "fsl,imx8qxp-iomuxc"; 217 218 pinctrl_lpuart0: lpuart0grp { 219 fsl,pins = < 220 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 221 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 222 >; 223 }; 224 ... 225 }; 226 227 ocotp: imx8qx-ocotp { 228 compatible = "fsl,imx8qxp-scu-ocotp"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 232 fec_mac0: mac@2c4 { 233 reg = <0x2c4 8>; 234 }; 235 }; 236 237 pd: imx8qx-pd { 238 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 239 #power-domain-cells = <1>; 240 }; 241 242 rtc: rtc { 243 compatible = "fsl,imx8qxp-sc-rtc"; 244 }; 245 246 scu_key: scu-key { 247 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 248 linux,keycodes = <KEY_POWER>; 249 }; 250 251 watchdog { 252 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 253 timeout-sec = <60>; 254 }; 255 256 tsens: thermal-sensor { 257 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 258 #thermal-sensor-cells = <1>; 259 }; 260 }; 261}; 262 263serial@5a060000 { 264 ... 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_lpuart0>; 267 clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 268 clock-names = "ipg"; 269 power-domains = <&pd IMX_SC_R_UART_0>; 270}; 271