1* Samsung Exynos7 Clock Controller
2
3Exynos7 clock controller has various blocks which are instantiated
4independently from the device-tree. These clock controllers
5generate and supply clocks to various hardware blocks within
6the SoC.
7
8Each clock is assigned an identifier and client nodes can use
9this identifier to specify the clock which they consume. All
10available clocks are defined as preprocessor macros in
11dt-bindings/clock/exynos7-clk.h header and can be used in
12device tree sources.
13
14External clocks:
15
16There are several clocks that are generated outside the SoC. It
17is expected that they are defined using standard clock bindings
18with following clock-output-names:
19
20 - "fin_pll" - PLL input clock from XXTI
21
22Required Properties for Clock Controller:
23
24 - compatible: clock controllers will use one of the following
25	compatible strings to indicate the clock controller
26	functionality.
27
28	- "samsung,exynos7-clock-topc"
29	- "samsung,exynos7-clock-top0"
30	- "samsung,exynos7-clock-top1"
31	- "samsung,exynos7-clock-ccore"
32	- "samsung,exynos7-clock-peric0"
33	- "samsung,exynos7-clock-peric1"
34	- "samsung,exynos7-clock-peris"
35	- "samsung,exynos7-clock-fsys0"
36	- "samsung,exynos7-clock-fsys1"
37	- "samsung,exynos7-clock-mscl"
38	- "samsung,exynos7-clock-aud"
39
40 - reg: physical base address of the controller and the length of
41	memory mapped region.
42
43 - #clock-cells: should be 1.
44
45 - clocks: list of clock identifiers which are fed as the input to
46	the given clock controller. Please refer the next section to
47	find the input clocks for a given controller.
48
49- clock-names: list of names of clocks which are fed as the input
50	to the given clock controller.
51
52Input clocks for top0 clock controller:
53	- fin_pll
54	- dout_sclk_bus0_pll
55	- dout_sclk_bus1_pll
56	- dout_sclk_cc_pll
57	- dout_sclk_mfc_pll
58	- dout_sclk_aud_pll
59
60Input clocks for top1 clock controller:
61	- fin_pll
62	- dout_sclk_bus0_pll
63	- dout_sclk_bus1_pll
64	- dout_sclk_cc_pll
65	- dout_sclk_mfc_pll
66
67Input clocks for ccore clock controller:
68	- fin_pll
69	- dout_aclk_ccore_133
70
71Input clocks for peric0 clock controller:
72	- fin_pll
73	- dout_aclk_peric0_66
74	- sclk_uart0
75
76Input clocks for peric1 clock controller:
77	- fin_pll
78	- dout_aclk_peric1_66
79	- sclk_uart1
80	- sclk_uart2
81	- sclk_uart3
82	- sclk_spi0
83	- sclk_spi1
84	- sclk_spi2
85	- sclk_spi3
86	- sclk_spi4
87	- sclk_i2s1
88	- sclk_pcm1
89	- sclk_spdif
90
91Input clocks for peris clock controller:
92	- fin_pll
93	- dout_aclk_peris_66
94
95Input clocks for fsys0 clock controller:
96	- fin_pll
97	- dout_aclk_fsys0_200
98	- dout_sclk_mmc2
99
100Input clocks for fsys1 clock controller:
101	- fin_pll
102	- dout_aclk_fsys1_200
103	- dout_sclk_mmc0
104	- dout_sclk_mmc1
105
106Input clocks for aud clock controller:
107	- fin_pll
108	- fout_aud_pll
109