1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MSM Display Port Controller 8 9maintainers: 10 - Kuogee Hsieh <khsieh@codeaurora.org> 11 12description: | 13 Device tree bindings for DisplayPort host controller for MSM targets 14 that are compatible with VESA DisplayPort interface specification. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sc7180-dp 20 - qcom,sc8180x-dp 21 - qcom,sc8180x-edp 22 23 reg: 24 items: 25 - description: ahb register block 26 - description: aux register block 27 - description: link register block 28 - description: p0 register block 29 - description: p1 register block 30 31 interrupts: 32 maxItems: 1 33 34 clocks: 35 items: 36 - description: AHB clock to enable register access 37 - description: Display Port AUX clock 38 - description: Display Port Link clock 39 - description: Link interface clock between DP and PHY 40 - description: Display Port Pixel clock 41 42 clock-names: 43 items: 44 - const: core_iface 45 - const: core_aux 46 - const: ctrl_link 47 - const: ctrl_link_iface 48 - const: stream_pixel 49 50 assigned-clocks: 51 items: 52 - description: link clock source 53 - description: pixel clock source 54 55 assigned-clock-parents: 56 items: 57 - description: phy 0 parent 58 - description: phy 1 parent 59 60 phys: 61 maxItems: 1 62 63 phy-names: 64 items: 65 - const: dp 66 67 operating-points-v2: 68 maxItems: 1 69 70 power-domains: 71 maxItems: 1 72 73 "#sound-dai-cells": 74 const: 0 75 76 ports: 77 $ref: /schemas/graph.yaml#/properties/ports 78 properties: 79 port@0: 80 $ref: /schemas/graph.yaml#/properties/port 81 description: Input endpoint of the controller 82 83 port@1: 84 $ref: /schemas/graph.yaml#/properties/port 85 description: Output endpoint of the controller 86 87required: 88 - compatible 89 - reg 90 - interrupts 91 - clocks 92 - clock-names 93 - phys 94 - phy-names 95 - "#sound-dai-cells" 96 - power-domains 97 - ports 98 99additionalProperties: false 100 101examples: 102 - | 103 #include <dt-bindings/interrupt-controller/arm-gic.h> 104 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 105 #include <dt-bindings/power/qcom-rpmpd.h> 106 107 displayport-controller@ae90000 { 108 compatible = "qcom,sc7180-dp"; 109 reg = <0xae90000 0x200>, 110 <0xae90200 0x200>, 111 <0xae90400 0xc00>, 112 <0xae91000 0x400>, 113 <0xae91400 0x400>; 114 interrupt-parent = <&mdss>; 115 interrupts = <12>; 116 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 117 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 118 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 119 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 120 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 121 clock-names = "core_iface", "core_aux", 122 "ctrl_link", 123 "ctrl_link_iface", "stream_pixel"; 124 125 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 126 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 127 128 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 129 130 phys = <&dp_phy>; 131 phy-names = "dp"; 132 133 #sound-dai-cells = <0>; 134 135 power-domains = <&rpmhpd SC7180_CX>; 136 137 ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 port@0 { 142 reg = <0>; 143 endpoint { 144 remote-endpoint = <&dpu_intf0_out>; 145 }; 146 }; 147 148 port@1 { 149 reg = <1>; 150 endpoint { 151 remote-endpoint = <&typec>; 152 }; 153 }; 154 }; 155 }; 156... 157